R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 309
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.5.7
Description
When FPSCR.PR = 0, this instruction loads floating-point 0.0 (0x00000000) into FRn.
If FPSCR.PR = 1, the instruction is handled as an illegal instruction.
Operation
Possible Exceptions:
None
PR
0
1
void FLDI0(int n)
{
}
Format
FLDI0 FRn
—
FR[n] = 0x00000000;
pc += 2;
FLDI0
0.0 Load
Abstract
0x00000000 → FRn
—
Floating-point
LoaD Immediate 0.0
Code
1111nnnn10001101 1
—
Rev. 3.00 Jul 08, 2005 page 293 of 484
Section 6 Instruction Descriptions
Floating-Point Instruction
Cycle
—
REJ09B0051-0300
T Bit
—
—
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