R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 320

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.5.12
Description
1. This instruction transfers FRm contents to FRn.
2. This instruction transfers DRm contents to DRn.
3. This instruction transfers FRm contents to memory at address indicated by Rn.
4. This instruction transfers DRm contents to memory at address indicated by Rn.
5. This instruction transfers contents of memory at address indicated by Rm to FRn.
6. This instruction transfers contents of memory at address indicated by Rm to DRn.
7. This instruction transfers contents of memory at address indicated by Rm to FRn, and adds 4 to
8. This instruction transfers contents of memory at address indicated by Rm to DRn, and adds 8
9. This instruction subtracts 4 from Rn, and transfers FRm contents to memory at address
10. This instruction subtracts 8 from Rn, and transfers DRm contents to memory at address
Rev. 3.00 Jul 08, 2005 page 304 of 484
REJ09B0051-0300
No. SZ Format
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. 1
11. 0
12. 1
13. 0
14. 1
Rm.
to Rm.
indicated by resulting Rn value.
indicated by resulting Rn value.
0
1
0
1
0
1
0
1
0
FMOV
FMOV
FMOV.S FRm,@Rn
FMOV.D DRm,@Rn
FMOV.S @Rm,FRn
FMOV.D @Rm,DRn
FMOV.S @Rm+,FRn
FMOV.D @Rm+,DRn
FMOV.S FRm,@-Rn
FMOV.D DRm,@-Rn
FMOV.S @(R0,Rm),FRn (R0+Rm) → FRn
FMOV.D @(R0,Rm),DRn (R0+Rm) → DRn
FMOV.S FRm, @(R0,Rn) FRm → (R0+Rn)
FMOV.D DRm, @(R0,Rn) DRm → (R0+Rn)
FMOV
Floating-Point
Transfer
FRm,FRn
DRm,DRn
Floating-point MOVe
Abstract
FRm → FRn
DRm → DRn
FRm → (Rn)
DRm → (Rn)
(Rm) → FRn
(Rm) → DRn
(Rm) → FRn,Rm+=4 1111nnnnmmmm1001 1
(Rm) → DRn,Rm+=8 1111nnn0mmmm1001 2
Rn-=4,FRm → (Rn) 1111nnnnmmmm1011 1
Rn-=8,DRm → (Rn) 1111nnnnmmm01011 2
Code
1111nnnnmmmm1100 1
1111nnn0mmm01100 2
1111nnnnmmmm1010 1
1111nnnnmmm01010 2
1111nnnnmmmm1000 1
1111nnn0mmmm1000 2
1111nnnnmmmm0110 1
1111nnn0mmmm0110 2
1111nnnnmmmm0111 1
1111nnnnmmm00111 2
Floating-Point Instruction
Cycle
T Bit
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