R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 363

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.3.4
An instruction that does not have one execution state is called a “multi-cycle instruction.” The
following rules apply to such instructions.
(1) When a multi-cycle instruction is executed as a preceding instruction, it cannot be executed in
(2) During execution of a multi-cycle instruction, if the slot is not the last slot, the next instruction
(3) At the end of the execution states of a multi-cycle instruction (in the last slot: equivalent to the
(4) A multi-cycle instruction can be executed in parallel with a preceding instruction that is a
(5) If a multicycle 32-bit instruction such as BAND.B, BANDNOT.B, BLD.B, BLDNOT.B,
MOV
MOVMU.L@R15+,R13
Multi-cycle instruction execution
in progress
Last multi-cycle instruction slot
ADD R2,R3
TST #imm,@(R0,GBR)
(Execution state 3)
MOVI20 #imm,R4
parallel with the succeeding instruction.
cannot be newly executed. “During execution” here refers to a slot not exceeding the number
of execution state cycles counting from the instruction ID stage.
execution state cycle), parallel execution with the next instruction is possible. Parallel
execution can be performed even if the next instruction is a 32-bit instruction.
single-cycle instruction (an instruction with one execution state).
A relevant example is shown in figure 8.26.
BOR.B, BORNOT.B, or BXOR is followed on the next line by the instruction BAND.B,
BANDNOT.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, or BXOR, the instruction on the
second line is executed in parallel (figure 8.27).
Details of Contention Due to Multi-Cycle Instruction
R5,R13
Figure 8.26 Example of Multi-Cycle Instruction Execution
Figure 8.25 Example of MOVMU.L Contention
IF
IF
IF
IF
ID
--
←  →
ID
ID
IF
EX
ID
EX
EX
—
EX
↔
MA
ID
MA
EX
EX
Rev. 3.00 Jul 08, 2005 page 347 of 484
MA
MA
Section 8 Pipeline Operation
WB
REJ09B0051-0300