R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 385

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Arithmetic
operation
instructions
Logical
operation
instructions
Type
Multiply-
and-
accumulate
instruction
Double-
precision
multiply-
and-
accumulate
instruction
Multiply
instructions
Double-
precision
multiply
instructions
DIVU
instruction
DIVS
instruction
Register-
register
logical
operation
instructions
Memory
logical
operation
instructions
TAS
instruction
Category
of Stages
Number
36
38
7
8
4
5
6
3
6
5
6
6
Execution
States
34
36
3
4
1
2
2
1
3
3
Latency
34
36
4
5
2
3
4
1
2
3
2
3
• This instruction
• This instruction
• These instruc-
• These instruc-
• These instruc-
• These instruc-
• This instruction
locks the
multiplier for 4
states.
locks the
multiplier for 5
states.
tions lock the
multiplier for 2
states.
tions lock the
multiplier for 2
states.
tions use the
shift register.
tions use the
memory access
pipeline.
uses the
memory access
pipeline.
Contention
Rev. 3.00 Jul 08, 2005 page 369 of 484
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Section 8 Pipeline Operation
MAC.W
MAC.L
MULS.W Rm,Rn
MULU.W Rm,Rn
DMULS.L Rm,Rn
DMULU.L Rm,Rn
MUL.L
MULR
DIVU
DIVS
AND
AND
NOT
OR
OR
TST
TST
XOR
XOR
AND.B
OR.B
TST.B
XOR.B
TAS.B
Instructions
REJ09B0051-0300
@Rm+,@Rn+
@Rm+,@Rn+
Rm,Rn
R0,Rn
R0,Rn
R0,Rn
Rm,Rn
#imm,R0
Rm,Rn
Rm,Rn
#imm,R0
Rm,Rn
#imm,R0
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
#imm,@(R0,GBR)
#imm,@(R0,GBR)
#imm,@(R0,GBR)
@Rn