R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 390

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
Single-
precision
floating-
point
instructions
Rev. 3.00 Jul 08, 2005 page 374 of 484
REJ09B0051-0300
Type
Floating-
point
register-
register
transfer
instructions
Floating-
point
register-
immediate
instructions
FSCHG
instruction
Floating-
point
register
load
instructions
Floating-
point
register
store
instructions
Category
of Stages
Number
5
5
5
5
4
4
Execution
States
1
1
1
1
1
1
1
Latency
0/2 *
1/2 *
0/2 *
0/2 *
1/0 *
0
0
1
0
0
3
3
3
3
3
• These instruc-
• These instruc-
• This instruction
• These instruc-
• This is 32-bit
• This instruction
• These instruc-
• This is 32-bit
• This instruction
tions use the
FPU load/store
pipeline.
tions use the
FPU load/store
pipeline.
uses the FPU
arithmetic
operation
pipeline.
tions use the
FPU load/store
pipeline and
memory access
pipeline.
instruction.
uses the FPU
load/store
pipeline and
memory access
pipeline.
tions use the
FPU load/store
pipeline and
memory access
pipeline.
instruction.
uses the FPU
load/store
pipeline and
memory access
pipeline.
Contention
FLDS
FMOV
FSTS
FLDI0
FLDI1
FSCHG
FMOV.S
FMOV.S
FMOV.S
FMOV.S
FMOV.S
FMOV.S
FMOV.S
FMOV.S
Instructions
FRm,FPUL
FRm,FRn
FPUL,FRn
FRn
FRn
@Rm,FRn
@Rm+,FRn
@(R0,Rm),FRn
@(disp12,Rm),FRn
FRm,@Rn
FRm,@-Rn
FRm,@ (R0,Rn)
FRm,@(disp12,Rn)