R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 417
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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R5S72030W200FP
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SAMSUNG
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(b) When a MULR instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
(c) When a MULR instruction is immediately followed by an STS (register) or STS.L (memory)
(d) When a MULR instruction is immediately followed by an LDS.L (memory) instruction
Instruction Issuance
This instruction uses the multiplier.
This instruction locks the multiplier for a 2-slot interval.
This instruction uses the multiplication result read path.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
(See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
MULR R0,Rn
MULR R0,Rn
Instruction after next
MULR R0,Rn
STS
Instruction after next
MULR R0,Rn
LDS.L @Rn+,MACL
Instruction after next
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the MULR instruction locks the multiplier, stalling occurs a further 1-slot interval back.
instruction
As the MULR instruction locks the multiplier, and multiplication result read path contention
occurs, stalling occurs a further 2-slot interval back.
Execution is delayed for a MULR instruction execution state (2-slot) interval.
MACL,Rn
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
IF
IF
IF
IF
ID
—
ID
—
ID
—
IF
IF
IF
mm
mm
mm
—
—
—
—
—
—
mm
mm
mm
ID
ID
—
—
ID
ID
mm
mm
mm
mm
EX
EX
EX
ID
ID
Rev. 3.00 Jul 08, 2005 page 401 of 484
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WB
WB
WB
MA
EX
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EX
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WB
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Section 8 Pipeline Operation
WB
REJ09B0051-0300
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