R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 45

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.7.4
When undefined code located other than immediately after a delayed branch instruction (in a delay
slot) is decoded, general illegal instruction exception handling is started. Also, in the case of a
product that does not have an FPU, or if the FPU is in the module standby state, a floating-point
instruction or FPU-related instruction is treated as undefined code, and if located other than
immediately after a delayed branch instruction (in a delay slot), will cause general illegal
instruction exception handling to be started when decoded. In addition, if the product that does
not have a register bank, register bank-related instructions are treated as undefined code. If not
located immediately after a delayed branch instruction (in a delay slot), when decoded they will
cause slot illegal instruction handling to be started.
The CPU follows the same procedure as in the case of slot illegal instruction exception handling,
except that the PC value saved is the start address of the undefined code.
3.7.5
An integer division exception is generated if an integer division instruction executes division by
zero, or if the result of integer division overflows. Instructions that may cause a division-by-zero
exception are DIVU and DIVS. The only instruction that may cause an overflow exception is
DIVS, the exception being generated if the negative maximum value is divided by –1. CPU
operations in integer division exception handling are as follows.
1. The start address of the exception service routine corresponding to the integer division
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the start address of the
4. Execution jumps to the address fetched from the exception handling vector table and program
3.7.6
An FPU exception is generated when the V, Z, O, U, or I bit in the enable field of the FPSCR
register is set. This indicates the occurrence of an invalid operation exception defined by the
IEEE754 standard, a division-by-zero exception, overflow (in the case of an instruction for which
this is possible), underflow (in the case of an instruction for which this is possible), or an
imprecision exception (in the case of an instruction for which this is possible).
Floating-point operation instructions that may cause an exception are as follows.
exception is fetched from the exception handling vector table.
integer division instruction that generated the exception.
execution commences. The jump is not a delayed branch.
General Illegal Instructions
Integer Division Instructions
Floating-Point Operation Instructions
Rev. 3.00 Jul 08, 2005 page 29 of 484
Section 3 Exception Handling
REJ09B0051-0300