R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 492

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
2. Counting Execution State Cycles
In this case, the result from the previously issued instruction is not used by the instructions that
follow it, so the instructions execute in parallel provided no resource contention occurs. The
number of cycles required by each instruction to execute are calculated in the “execution state.”
When the preceding instruction uses one execution state cycle, the following instruction executes
in parallel. When parallel execution takes place, the number of cycles required by the preceding
instruction is calculated as “execution state” minus one. This serves as a simplified compensation.
(This compensation appears as the final item in the equation introduced below.)
3. If Resource Contention Occurs
If resource contention occurs, parallel execution is not possible. The execution of each instruction
requires “execution state” cycles.
4. Instructions Using More Than One Execution State
For instructions using more than one execution state, the calculation assumes that the number of
remaining states is reduced one by one until only one remains, at which point parallel execution
with the subsequent instructions is possible. In this case, the number of cycles required for
execution is calculated as “execution state” minus one if parallel execution with subsequent
instructions takes place, and as “execution state” if no parallel execution takes place. This serves
Rev. 3.00 Jul 08, 2005 page 476 of 484
REJ09B0051-0300
MOV.L
ADD
MOV.L
MOV.L
MOV.L
MOV.L
AND.B # imm, @(R0,GBR)
ADD
BAND.B # imm, @(disp12,R2)
ROTCL
# imm, R1
@ R1, R0
R3, @ R4
@ R1, R0
@ R3, R2
@ R5, R4
# imm, R2
↔
↔
↔
↔
↔
↔
ID
ID
ID
ID
↔
↔
↔
EX
EX
EX
EX
ID
ID
↔
↔
↔
MA
MA
MA
EX
EX
ID
ID
↔
↔
↔
WB
MA
WB
MA
EX
EX
EX
ID
↔
↔
↔
WB
MA
EX
↔
↔
↔
WB
MA
↔
↔
↔
EX
ID
Cycles
Cycles
Cycles
1→0
3→2
1
1
1
1
3