R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 54

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Instruction Features
Rev. 3.00 Jul 08, 2005 page 38 of 484
REJ09B0051-0300
Addressing
Mode
Indirect
register
addressing
with
displace-
ment
Indirect
indexed
register
addressing
Indirect
GBR
addressing
with
displace-
ment
Instruction
Format
@(disp:4,
Rn)
@(disp:12,
Rn)
@(R0, Rn)
@(disp:8,
GBR)
Effective Addresses Calculation
The effective address is Rn plus a 4-bit displacement
(disp). The value of disp is zero-extended, and
remains the same for a byte operation, is doubled for
a word operation, or is quadrupled for a longword
operation.
Effective address is register Rn contents with 12-bit
displacement disp added. disp is zero-extended.
The effective address is the Rn value plus R0.
The effective address is the GBR value plus an 8-bit
displacement (disp). The value of disp is zero-
extended, and remains the same for a byte
operation, is doubled for a word operation, or is
quadrupled for a longword operation.
(zero-extended)
(zero-extended)
(zero-extended)
1/2/4
Rn
R0
disp
GBR
1/2/4
disp
disp
Rn
Rn
+
+
+
+
+ disp
+ disp
Rn + R0
Rn + disp
GBR
Rn
1/2/4
1/2/4
Formula
Byte: Rn +
disp
Word: Rn +
disp × 2
Longword:
Rn + disp × 4
Byte: Rn +
disp
Word: Rn +
disp
Longword:
Rn + disp
Rn + R0
Byte: GBR +
disp
Word: GBR +
disp × 2
Longword:
GBR + disp ×
4