R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 59

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5S72030W200FP
Manufacturer:
RENESAS
Quantity:
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Instruction Formats
nm format
md format
nd4 format
nmd format
15
15
15
15
xxxx
xxxx
xxxx
xxxx
nnnn
nnnn
xxxx
xxxx
mmmm
mmmm
mmmm
nnnn
dddd
dddd
xxxx
dddd
0
0
0
0
Source
Operand
mmmm: Direct
register
mmmm: Direct
register
mmmm: Indirect
post-increment
register
(multiply/
accumulate)
nnnn * : Indirect
post-increment
register
(multiply/
accumulate)
mmmm: Indirect
post-increment
register
mmmm: Direct
register
mmmm: Direct
register
mmmmdddd:
indirect register
with
displacement
R0 (Direct
register)
mmmm: Direct
register
mmmmdddd:
Indirect register
with
displacement
Destination
Operand
nnnn: Direct
register
nnnn: Indirect
register
MACH, MACL
nnnn: Direct
register
nnnn: Indirect pre-
decrement register
nnnn: Indirect
indexed register
R0 (Direct register) MOV.B
nnnndddd: Indirect
register with
displacement
nnnndddd: Indirect
register with
displacement
nnnn: Direct
register
Rev. 3.00 Jul 08, 2005 page 43 of 484
Section 4 Instruction Features
Example
ADD Rm,Rn
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L
Rm,@(R0,Rn)
@(disp,Rm),R0
MOV.B
R0,@(disp,Rn)
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
REJ09B0051-0300

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