R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 92

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
Rev. 3.00 Jul 08, 2005 page 76 of 484
REJ09B0051-0300
unsigned
unsigned
unsigned
unsigned
unsigned
Data Data is written to address Addr using the respective size. A word write to other than a 2n address or a
longword write to other than a 4n address will be detected as an address error.
unsigned
Data);
Data Data is written to the register bank entry indicated by the contents of address Addr.
unsigned
unsigned
unsigned
unsigned
Respective registers
struct
} ;
BANK
Register bank structure definition
(VTO: Interrupt vector table address offset)
struct SR0 {
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
Register_Bank[512];
BANK {
char
short
int
long
double
long
long
long
long
long
long
long
long
long
long
long
long
long
long
long
long
long
long
Write_Bank_Long (unsigned
R[16];
SR, GBR, VBR, TBR;
MACH, MACL, PR;
PC;
Write_Byte (unsigned long Addr, unsigned long Data);
Write_Word (unsigned long Addr, unsigned long Data);
Write_Int (unsigned long Addr, unsigned long Data);
Write_Long (unsigned long Addr, unsigned long Data);
Write_Quad (unsigned long Addr, unsigned long Data);
Rn_BANK[15];
GBR_BANK;
MACH_BANK;
MACL_BANK;
PR_BANK;
IVN;
dummy0:17;
BO0:1
CS0:1;
dummy1:3;
M0:1;
Q0:1;
I0:4;
long Add, unsigned long