MAX791CPE+ Maxim Integrated Products, MAX791CPE+ Datasheet - Page 9
![IC MPU SUPERVISORY CIRCUIT 16DIP](/photos/6/57/65728/175-16-dip_sml.jpg)
MAX791CPE+
Manufacturer Part Number
MAX791CPE+
Description
IC MPU SUPERVISORY CIRCUIT 16DIP
Manufacturer
Maxim Integrated Products
Type
Battery Backup Circuitr
Datasheet
1.MAX791CSE.pdf
(19 pages)
Specifications of MAX791CPE+
Number Of Voltages Monitored
1
Output
Push-Pull, Totem Pole
Reset
Active Low
Reset Timeout
140 ms Minimum
Voltage - Threshold
4.65V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Monitored Voltage
4.65 V
Undervoltage Threshold
4.5 V
Overvoltage Threshold
4.75 V
Manual Reset
Resettable
Watchdog
Yes
Battery Backup Switching
Yes
Power-up Reset Delay (typ)
280 ms
Supply Voltage (max)
5.5 V
Supply Voltage (min)
0 V
Supply Current (typ)
150 uA
Maximum Power Dissipation
842 mW
Mounting Style
Through Hole
Maximum Operating Temperature
+ 70 C
Chip Enable Signals
Yes
Minimum Operating Temperature
0 C
Output Type
Active Low or Open Drain or Push-Pull
Power Fail Detection
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 4. Adding an External Pull-Down Resistor Ensures
–
R
The MAX791’s RESET output ensures that the µP pow-
ers up in a known state, and prevents code-execution
errors during power-down or brownout conditions.
The RESET output is active low, and typically sinks
3.2mA at 0.1V saturation voltage in its active state.
When deasserted, RESET sources 1.6mA at typically
V
output is guaranteed to be valid down to V
an external 10kΩ pull-down resistor on RESET ensures
that RESET will be valid with V
4). As V
output switch reduces accordingly, increasing the
r
resistor ensures the parallel combination of switch plus
resistor is around 10kΩ and the output saturation volt-
age is below 0.4V while sinking 40µA. When using a
10kΩ external pull-down resistor, the high state for the
RESET output with V
voltages ≥ 2V connected to VBATT, RESET remains
valid for V
RESET will be asserted during the following conditions:
The MAX791 battery-switchover comparator does not
affect RESET assertion. However, RESET is asserted in
battery-backup mode since V
reset threshold to enter this mode.
The watchdog monitors µP activity via the Watchdog
Input (WDI). If the µP becomes inactive, WDO and
WDPO are asserted. To use the watchdog function,
connect WDI to a bus line or µP I/O line. If WDI remains
—
DS(ON)
•
•
•
E
—
OUT
S
—
E
—
T
–
V
MR < 1.25V (typ).
RESET remains asserted for 200ms (typ) after V
rises above 4.65V or after MR has exceeded
1.25V.
- 0.5V. When no backup battery is used, RESET
CC
is Valid with V
CC
and the saturation voltage. The 10kΩ pull-down
< 4.65V (typ).
CC
goes below 1V, the gate drive to the RESET
MAX791
from 0V to 5.5V.
_______________________________________________________________________________________
RESET
CC
CC
Down to GND
15
= 4.75V is 4.5V typ. For battery
Microprocessor Supervisory Circuit
CC
Watchdog Function
10k
CC
down to GND (Figure
must be below the
TO µP RESET
RESET Output
CC
= 1V, and
CC
high or low for longer than the watchdog timeout period
(1.6s nominal), WDPO and WDO are asserted, indicat-
ing a software fault condition (see Watchdog Output
and Watchdog-Pulse Output sections).
A change of state (high to low, low to high, or a mini-
mum 100ns pulse) at WDI during the watchdog period
resets the watchdog timer. The watchdog default time-
out is 1.6s. Select alternative timeout periods by con-
necting an external capacitor from SWT to GND (see
Selecting an Alternative Watchdog Timeout Period sec-
tion).
To disable the watchdog function, leave WDI floating.
An internal resistor network (100kΩ equivalent imped-
ance at WDI) biases WDI to approximately 1.6V.
Internal comparators detect this level and disable the
watchdog timer. When V
old, the watchdog function is disabled and WDI is dis-
connected from its internal resistor network, thus
becoming high impedance.
WDO remains high if there is a transition or pulse at
WDI during the watchdog-timeout period. The watch-
dog function is disabled and WDO is a logic high when
V
is enabled, or WDI is an open circuit. In watchdog
mode, if no transition occurs at WDI during the watch-
dog-timeout period, WDO goes low 70ns after the
falling edge of WDPO and remains low until the next
transition at WDI (Figure 5). A flip-flop can force the
system into a hardware shutdown if there are two suc-
cessive watchdog faults (Figure 6). WDO has a 2 x TTL
output characteristic.
Figure 5. WDI,
CC
WDPO
WDO
WDI
is below the reset threshold, battery-backup mode
–
W
—
D
—
O
–
, and
–
W
—
70ns
D
—
CC
P
—
1.6s
O
–
is below the reset thresh-
Timing Diagram (V
Watchdog Output
Watchdog Input
100ns MIN
CC
Mode)
9