X40421V14I-B Intersil, X40421V14I-B Datasheet
X40421V14I-B
Specifications of X40421V14I-B
Related parts for X40421V14I-B
X40421V14I-B Summary of contents
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... CC Logic CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. X40420, X40421 4kbit EEPROM FN8117.1 Level Standard V Level Suffix TRIP2 2.9V(± ...
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... X40421S14I-B X40421S IB X40420S14IZ-B X40420S ZIB X40421S14IZ-B (Note) (Note) X40420V14-B X4042 0VB X40421V14-B X40420V14Z-B X4042 0VZB X40421V14Z-B (Note) (Note) X40420V14I-B X4042 0VIB X40421V14I-B X40421V IB X40420V14IZ-B X4042 0VZIB X40421V14IZ-B (Note) (Note) X40420S14-A X40420S A X40421S14-A X40420S14Z-A X40420S ZA X40421S14Z-A (Note) (Note) X40420S14I-A X40420S IA X40421S14I-A X40421S IA ...
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... EEPROM array with Intersil’s Block Lock protection. The array is internally organized The device features an 2-wire interface and software protocol allowing operation on a two-wire bus. The device utilizes Intersil’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Example Application Unreg ...
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PIN DESCRIPTION (Continued) Pin Name 6 RESET/ RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever RESET V falls below V CC grammed time period (t for t thereafter. PURST RESET Output. (X40420) ...
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PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40420, X40421 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. ...
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Figure 3. V Set/Reset Conditions TRIPX V TRIPX WDO 0 SCL SDA A0h Figure 4. Watchdog Restart .6µs 1.3µs SCL SDA Start WDT Reset V1 AND V2 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40420, X40421 is shipped with standard V1 and ...
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Resetting the V Voltage TRIPx To reset a V voltage, apply the programming volt- TRIPx age (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h ...
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Figure 6. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory ...
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BP: Block Protect Bit (Nonvolatile) The Block Protect Bits BP determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bit will prevent write operations to half the ...
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Figure 7. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the ...
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Figure 8. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indi- cate successful data transfer. The transmitting device, either master or slave, will release the bus after trans- mitting eight bits. During ...
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Figure 10. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but ...
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Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is issued in the middle of a data ...
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A similar operation called “Set Current Address” where the device will perform this operation if a stop is issued instead of the second start is shown in Figure 15. The device will go into standby mode after the stop and ...
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Figure 15. Random Address Read Sequence S t Signals from a the Master r t SDA Bus Signals from the Slave Figure 16. X40410/11 Addressing Slave Byte General Purpose Memory Control Register 1 0 ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C ...
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter (7) V Schmitt Trigger Input Hysteresis HYS • Fixed input level V • related level CC V Output LOW Voltage (SDA, RESET/ OL RESET, LOWLINE, V2FAIL, WDO) ...
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CAPACITANCE Symbol (1) C Output Capacitance (SDA, RESET, RESET/LOWLINE, OUT V2FAIL, WDO) (1) C Input Capacitance (SCL, WP) IN Note: (1) This parameter is not 100% tested. EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT ...
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A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time ...
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WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a ...
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RESET/RESET/MR Timings V TRIP1 PURST t R RESET V RVALID RESET MR LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Symbol ( RESET/RESET (Power-down only) RPD1 TRIP1 LOWLINE RPDL ...
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Watchdog Time Out For 2-Wire Interface Start Clockin ( SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start 22 X40420, X40421 ...
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Programming Specifications: V TRIP1 TRIP2 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t V ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...