AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 331
AT91SAM7S256C-MU
Manufacturer Part Number
AT91SAM7S256C-MU
Description
IC ARM7 MCU 32BIT 256K 64-QFN
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM7S16-MU.pdf
(51 pages)
2.AT91SAM7S16-MU.pdf
(779 pages)
3.AT91SAM7S256C-MU.pdf
(2 pages)
Specifications of AT91SAM7S256C-MU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT91
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S256-MU
AT91SAM7S256-MU
AT91SAM7S256-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S256C-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 331 of 779
- Download datasheet (11Mb)
Figure 30-20. Programmer Sends Data While the Bus is Busy
Figure 30-21. Arbitration Cases
6175K–ATARM–30-Aug-10
Data from a Master
TWI DATA transfer
TWI DATA transfer
Data from TWI
(DADR + W + START + Write THR)
(DADR + W + START + Write THR)
ARBLST
TWCK
A transfer is programmed
TWCK
TWD
TWD
A transfer is programmed
TWCK
TWD
Note:
The flowchart shown in
in Multi-master mode.
S
S
S
In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it
is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat
SADR.
DATA sent by a master
1
1
1
Transfer is stopped
Bus is busy
0 0
0
0 0
1
STOP sent by the master
Transfer is kept
1 1
1 1
TWI stops sending data
Arbitration is lost
Figure 30-22 on page 332
(DADR + W + START + Write THR)
Transfer is programmed again
Data from the master
Bus is busy
Transfer is kept
AT91SAM7S Series Preliminary
Bus is free
Bus is considered as free
Transfer is initiated
P
P
Bus is free
gives an example of read and write operations
Bus is considered as free
Transfer is initiated
START sent by the TWI
S
S
S
1
1
1
0
0 0
0
DATA sent by the TWI
1
0
1 1
The master stops sending data
1 1
Arbitration is lost
Data from the TWI
331
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