MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 101

IC MCU 8BIT 8K FLASH 48-LQFP

MC68908GZ8MFAE

Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68908GZ8MFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
8.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
8.5 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during
the break state. See
To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE bit. With BCFE at logic
0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has
no effect on the IRQ interrupt flags.
Freescale Semiconductor
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK
bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that
poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK
bit another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ remains active.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
Chapter 20 Development
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Support.
NOTE
IRQ Pin
101

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