MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 204

• Manufacturer Part Number: MC68908GZ8MFAE
• Description: IC MCU 8BIT 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Enhanced Serial Communications Interface (ESCI) Module
15.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the ESCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
15.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
LINT — LIN Transmit Enable
LINR — LIN Receiver Bits
204
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register.
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
Address:
Address:
Do not use read-modify-write instructions on the ESCI data register.
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Table
Table
Reset:
Reset:
Read:
Read:
Write:
Write:
15-6. Reset clears LINT.
15-6. Reset clears LINR.
$0018
$0019
LINT
Bit 7
Bit 7
R7
T7
R
0
Figure 15-17. ESCI Baud Rate Register (SCBR)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Figure 15-16. ESCI Data Register (SCDR)
= Reserved
LINR
R6
T6
6
6
0
SCP1
R5
T5
5
5
0
NOTE
NOTE
Unaffected by reset
SCP0
R4
T4
4
4
0
R3
T3
R
3
3
0
SCR2
R2
T2
2
2
0
SCR1
R1
T1
1
1
0
Freescale Semiconductor
SCR0
Bit 0
Bit 0
R0
T0
0