MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 72

• Manufacturer Part Number: MC68908GZ8MFAE
• Description: IC MCU 8BIT 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Clock Generator Module (CGM)
LOCK — Lock Indicator Bit
ACQ — Acquisition Mode Bit
4.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
MUL11–MUL8 — Multiplier Select Bits
PMSH[7:4] — Unimplemented Bits
72
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. The write one function of this bit is reserved for test, so this bit must always be
written a 0. Reset clears the LOCK bit.
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
These bits have no function and always read as logic 0s.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
1 = Tracking mode
0 = Acquisition mode
Address:
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
Reset:
Read:
Write:
Figure 4-6. PLL Multiplier Select Register High (PMSH)
$0038
Bit 7
0
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
= Unimplemented
4.3.3 PLL Circuits
6
0
0
5
0
0
NOTE
and
4
0
0
4.3.6 Programming the
MUL11
3
0
MUL10
2
0
MUL9
PLL.) A value of $0000 in
1
0
Freescale Semiconductor
MUL8
Bit 0
0