MCR908JL3ECDWE Freescale Semiconductor, MCR908JL3ECDWE Datasheet - Page 116
MCR908JL3ECDWE
Manufacturer Part Number
MCR908JL3ECDWE
Description
IC MCU 4K FLASH 8MHZ 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MCR908JL3ECDWE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Processor Series
HC08JL
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCR908JL3ECDWE
Manufacturer:
Zilog
Quantity:
65
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External Interrupt (IRQ)
11.5 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR has the following functions:
IRQF — IRQ Flag
ACK — IRQ Interrupt Request Acknowledge Bit
IMASK — IRQ Interrupt Mask Bit
MODE — IRQ Edge/Level Select Bit
IRQPUD — IRQ Pin Pull-up control bit
116
•
•
•
•
This read-only status bit is high when the IRQ interrupt is pending.
Writing a one to this write-only bit clears the IRQ latch. ACK always reads as zero. Reset clears ACK.
Writing a one to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and V
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ and interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
POR:
IRQPUD
Figure 11-3. IRQ Status and Control Register (INTSCR)
$001D
$001E
Bit 7
Bit 7
R
0
0
0
0
Figure 11-4. Configuration Register 2 (CONFIG2)
= Unimplemented
= Reserved
MC68HC908JL3E Family Data Sheet, Rev. 4
R
6
0
0
6
0
0
R
5
0
0
5
0
0
Not affected Not affected
LVIT1
4
0
0
4
0
LVIT0
IRQF
3
0
3
0
DD
ACK
R
2
0
2
0
0
IMASK
R
1
0
1
0
0
Freescale Semiconductor
MODE
Bit 0
Bit 0
R
0
0
0
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