TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 303
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 303 of 744
- Download datasheet (8Mb)
9.4.2
31-2
1
0
DMACCxConfiguration<ITC>
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
DMACCxConfiguration<IE>
Bit
-
IntStatus1
IntStatus0
DMACIntStatus (DMAC Interrupt Status Register)
DMA terminal count
Bit Symbol
DMA transfer error
Undefined
Undefined
Undefined
Undefined
31
23
15
7
-
-
-
-
W
R
R
Type
Undefined
Undefined
Undefined
Undefined
30
22
14
Figure 9-2 Interrupt-related block diagram
6
Write as zero.
Status of DMAC channel 1 transfer end interrupt.
0 : Interrupt not requested
1 : Interrupt requested
Status of the DMAC interrupt generation after passing through the transfer end interrupt enable register
and error interrupt enable register. An interrupt is requested when there is a transfer error or when the coun-
ter completes counting.
Status of DMAC channel 0 interrupt generation.
0 : Interrupt not requested
1 : Interrupt requested
Status of the DMAC interrupt generation after passing through the transfer end interrupt enable register
and error interrupt enable register. An interrupt is requested when there is a transfer error or when the coun-
ter completes counting.
-
-
-
-
Undefined
Undefined
Undefined
Undefined
29
21
13
5
-
-
-
-
Page 279
Undefined
Undefined
Undefined
Undefined
28
20
12
4
-
-
-
-
DMACIntTCStatus (Masked terminal count interrupt)
DMACIntErrorStatus (Masked transfer error interrupt)
DMACIntStatus
DMACRawIntTCStatus (Terminal count interrupt prior to masking)
DMACRawIntErrorStatus (Transfer error interrupt prior to masking)
Undefined
Undefined
Undefined
Undefined
Description
27
19
11
3
-
-
-
-
Undefined
Undefined
Undefined
Undefined
26
18
10
2
-
-
-
-
Undefined
Undefined
Undefined
IntStatus1
25
17
9
1
0
-
-
-
TMPM362F10FG
Undefined
Undefined
Undefined
IntStatus0
24
16
8
0
0
-
-
-
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