XR88C681J-F Exar Corporation, XR88C681J-F Datasheet - Page 53

IC UART CMOS DUAL 44PLCC

XR88C681J-F

Manufacturer Part Number
XR88C681J-F
Description
IC UART CMOS DUAL 44PLCC
Manufacturer
Exar Corporation
Type
CMOS Dual Channel UARTr
Datasheet

Specifications of XR88C681J-F

Number Of Channels
2, DUART
Package / Case
44-LCC (J-Lead)
Features
*
Fifo's
1 Byte, 3 Byte
Voltage - Supply
5V
With Parallel Port
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
1 Mbps
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Supply Current
15 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Propagation Delay Time Ns
400 ns
No. Of Channels
2
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
PLCC
No. Of Pins
44
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1329

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Manufacturer
Quantity
Price
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XR88C681J-F
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Part Number:
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Manufacturer:
Exar Corporation
Quantity:
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D.2 Bit Rate Generator
The BRG (Bit Rate Generator) accepts the timing output
of the Oscillator Circuit and generate the clock signal for
23 commonly used data communication bit rates ranging
from 50 bps up to 115.2kbps. Please note that the BRG
will only generate these standard bit rates if the Oscillator
Circuit is running at 3.6864 MHz. Additionally, the actual
Rev. 2.11
X1/CLK
Figure 27. Block Diagram of the Bit Rate Generator portion of the Timing Control Block
X2
Oscillator
Circuit
Bit Rate Generator
Channels A and B
ACR[7]
53
clock frequencies output from the BRG are at 16 times
these rates.
The user can select one of two different sets of bit rates, to
be generated from the BRG. This selection is made by
setting or clearing ACR[7]. A listing of these sets of Bit
Rates, from the BRG, is presented in the discussion of the
Clock Select Registers (CSRs) in Section D.5. A block
diagram of the BRG circuitry is presented in Figure 27.
CSRA[7:4]
32:1 MUX
CSRB[3:0]
32:1 MUX
CSRA[3:0]
32:1 MUX
CSRB[7:4]
32:1 MUX
XR88C681
RXCA
TXCA
TXCB
RXCB

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