ST16C654DIQ64-F Exar Corporation, ST16C654DIQ64-F Datasheet - Page 35
![IC UART FIFO 64B QUAD 64LQFP](/photos/29/6/290652/lqfp64_sml.jpg)
ST16C654DIQ64-F
Manufacturer Part Number
ST16C654DIQ64-F
Description
IC UART FIFO 64B QUAD 64LQFP
Manufacturer
Exar Corporation
Datasheet
1.ST16C654CJ68-F.pdf
(51 pages)
Specifications of ST16C654DIQ64-F
Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS232
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
1.5 Mbps
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
4
Uart Features
Infrared (IrDA) Encoder/Decoder
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1271
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST16C654DIQ64-F
Manufacturer:
Exar
Quantity:
54
Company:
Part Number:
ST16C654DIQ64-F
Manufacturer:
Exar Corporation
Quantity:
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Part Number:
ST16C654DIQ64-F
Manufacturer:
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xr
REV. 5.0.2
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at the next upper trigger level/hysteresis level. RTS# will return to a logic 0 when
FIFO data falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (logic 0)
before the auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow
control is disabled.
•
•
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•
•
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
This register is applicable only to the 100 pin QFP ST16C654. The FIFO Status Register provides a status
indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the
TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the
FSTAT register are placed on the data bus when the FSRS# pin (pin 76) is a logic 0. Also see FSRS# pin
description.
FSTAT[3:0]: TXRDY# A-D Status Bits
Please see
FSTAT[7:4]: RXRDY# A-D Status Bits
Please see
4.13
4.14
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
FIFO Status Register (FSTAT) - Read/Write
Table 5
Table 5
for the interpretation of the TXRDY# signals.
for the interpretation of the RXRDY# signals.
Table
8.
35
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
ST16C654/654D