EM250-DEV Ember, EM250-DEV Datasheet - Page 23

• Manufacturer Part Number: EM250-DEV
• Description: KIT DEV FOR EM250
• Manufacturer: Ember
• Series: InSightr
• Type: 802.15.4/Zigbeer

Specifications of EM250-DEV

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 636-1002

4.8
4.9
4.10 Clock Sources
Reset Detection
Power-on-Reset (POR)
The EM250 contains multiple reset sources. The reset event is logged into the reset source register, which lets
the CPU determine the cause of the last reset. The following reset causes are detected:
Each voltage domain (1.8V Digital Core Supply VDD_CORE and Pads Supply VDD_PADS) has a power-on-reset
(POR) cell.
The VDD_PADS POR cell holds the always-powered high-voltage domain in reset until the following conditions
have been met:
Additionally, the digital domain counts 1,024 clock edges on the 24MHz crystal before releasing the reset to
the main digital core.
Table 11 lists the features of the EM250 POR circuitry.
Parameter
VDD_PADS POR release
VDD_PADS POR assert
1.8V POR release
1.8V POR hysteresis
The EM250 integrates three oscillators: a high-frequency 24MHz crystal oscillator, an optional low-frequency
32.768kHz crystal oscillator, and a low-frequency internal 10kHz RC oscillator.
4.10.1 High-Frequency Crystal Oscillator
The integrated high-frequency crystal oscillator requires an external 24MHz crystal with an accuracy of
±40ppm. Based upon the application Bill of Materials and current consumption requirements, the external
crystal can cover a range of ESR requirements. For a lower ESR, the cost of the crystal increases but the over-
all current consumption decreases. Likewise, for higher ESR, the cost decreases but the current consumption
increases. Therefore, the designer can choose a crystal to fit the needs of the application.
Power-on-Reset
Watchdog
PC rollover
Software reset
Core Power Dip
The high-voltage Pads Supply VDD_PADS voltage rises above a threshold.
The internal RC clock starts and generates three clock pulses.
The 1.8V POR cell holds the main digital core in reset until the regulator output voltage rises above a
threshold.
Table 11. POR Specifications
Min.
1.0
0.5
1.35
0.08
Typ.
1.2
0.6
1.5
0.1
120-0082-000I
Max.
1.4
0.7
1.65
0.12
EM250
Unit
V
V
V
V
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