AT86RF211SAH-R Atmel, AT86RF211SAH-R Datasheet - Page 31

• Manufacturer Part Number: AT86RF211SAH-R
• Description: IC RF TXRX FSK 400-950MHZ 48TQFP
• Manufacturer: Atmel

Specifications of AT86RF211SAH-R

• Frequency: 400MHz ~ 950MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dBm ~ 12dBm
• Sensitivity: -107dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -

2.3.5
Figure 2-27. Benefits of Resynchronization
5348B–WIRE–03/06
Data Resynchronization
DATAMSG
DATACLK
Center of
Case No. 1: no resynchronization
bit
Figure 2-26. Clock Recovery Target Position
Note:
As the AT86RF211S can provide a synchronization signal together with the demodu-
lated data on pins DATAMSG and DATACLK, it is also possible to “re-shape” the data
received.
In resynchronization mode the signals provided to the companion MCU are filtered; the
jitter of the generated clock remains the only concern. The bit decision is then fully per-
formed on the chip, thus removing real-time constrainsts on the MCU. This facilitates the
data transfer, independently of the chosen protocol (UART, USART, SPI etc.)
Note:
Figure 2-27 shows that the data provided to the MCU has a perfect bit period, with the
synchronization clock centered on the half bit.
median
Clock
time
uncertainty
First random position of
clock's rising edge
Use the above settings to ensure a good trade-off between the settling time and the jitter
of the clock. The clock remains correct, regardless of the number of transitions in the
received stream, as long as the reference clocks of Tx and Rx are the same. Example: if
D (Rx - Tx) = 20 ppm, the clock is centered at ±20% for at least 0.2/20.10
Resynchronizations add a short latency time on the data; this does not affect
transmission.
Clock
DATAMSG
DATACLK
Target position of
clock's rising edge
reception quality
depending on
Data jitter
1 x Tol
Case No. 2: resynchronization
50%
Uncertainty area
+/- 10% max.
Center of bit
+/- Tol = uncertainty
50%
AT86RF211S
-6
= 10 kbits.
31