SI4205-BM Silicon Laboratories Inc, SI4205-BM Datasheet
SI4205-BM
Specifications of SI4205-BM
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SI4205-BM Summary of contents
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... PGA DAC I PGA ADC PGA DAC Q XOUT 100 kHz I DET Q VC-TCXO MHz IF XIN AFC PLL Copyright © 2003 by Silicon Laboratories Pin Assignments (Top View) Si4205-BM (For pin description see page 33 RFIGN RXQN 21 1 RFIGP RXIP 2 20 GND GND GND RFIDN RXIN ...
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Aero I 2 Rev. 1.0 ...
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... Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Descriptions: Si4205- .33 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package Outline: Si4205- .35 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Rev. 1.0 Aero I Page 3 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The Si4205 device is high-performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. ...
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Table 3. DC Characteristics (V = 2 – ° Parameter 1 Supply Current 2 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Input Current 2 Low Level ...
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Aero I Table 4. AC Characteristics (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time PDN Rise Time PDN ...
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SCLK 50% 20% Figure 1. SCLK Timing Diagram t PR 80% PDN 20% Figure 2. PDN Timing Diagram 80% D17 D16 50% SDI 20 HOLD 80% 50% SCLK 20 ...
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Aero I Table 5. Receiver Characteristics (V = 2 – ° Parameter 1 GSM Input Frequency 1 DCS or PCS Input Frequency 2,3 Noise Figure ° 2,3 Noise ...
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Table 5. Receiver Characteristics (Continued 2 – ° Parameter Analog PGA Control Range Analog PGA Step Size Digital PGA Control Range Digital PGA Step Size Maximum Differential Output Voltage ...
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Aero I Receive Path Magnitude Response (CSEL = 0) 0 −20 −40 −60 −80 −100 −120 0 50 100 150 200 250 Frequency (KHz) Figure 5. Receive Path Magnitude Response (CSEL = 0 and CSEL = 1) Receive Path Passband ...
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Table 6. Transmitter Characteristics (V = 2 – ° Parameter 1 RFOG Output Frequency 2 RFOD Output Frequency 3,4 I/Q Differential Input Swing 3 I/Q Input Common-Mode 3,4 I/Q Differential Input ...
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Aero I Table 6. Transmitter Characteristics (Continued 2 – ° Parameter 1,2 RF Output Harmonic Suppression 5,8 Powerup Settling Time Notes: 1. Measured at RFOG pin. 2. Measured at ...
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Table 7. Frequency Synthesizer Characteristics (V = 2 – ° Parameter 1 RF1 VCO Frequency 1 RF2 VCO Frequency 1 IF VCO Frequency RF1 PLL Phase Detector Update Frequency IF and ...
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... Detailed SAW filter requirements. 3. For the XIN input, no external ac coupling is required. 4. For optimum performance, connect pin 31 to ground plane of power amplifier through several vias close to pin GND 21 RFIGN 20 RFIGP U1 19 RFIDN C3 18 RFIDP Si4205 17 RFIPN 16 RFIPP 15 GND L2 30 GND Rev. 1.0 RFOG RFOD Z1 GSM900 IN ...
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... Murata LQG15HN series (0402 size) Murata LQW15AN series (0402 size) Murata LQG15HN series (0402 size) Murata LQW15AN series (0402 size) Silicon Laboratories Si4205 Epcos B39881-B9001-C710 (5-pin, 1.4 x 2.0 mm) Epcos B39881-B9004-E710 (6-pin, 1.6 x 2.0 mm) Murata SAFEK881MFL0T00R00 (6-pin, 1.6 x 2.0 mm) Epcos B39941-B7820-C710 (5-pin, 1.4 x 2.0 mm) Epcos B39941-B9017-K310 (6-pin, 1 ...
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... While conventional solutions use BiCMOS or other voice and data bipolar process technologies, the Aero I transceiver employs 100% CMOS process. This brings the dramatic cost savings and extensive manufacturing capacity of CMOS to the GSM market. interface is Rev. 1.0 Si4205 PGA DAC I PGA DAC Q XOUT 100 kHz I Q ...
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... I/Q pins can be multiplexed together into a 4- wire interface. The common mode level at the receive I and Q outputs is programmable with the DACCM[1:0] bits, and the full scale level is programmable with the DACFS[1:0] bits in register 12h. Rev. 1.0 Aero I Si4205 DAC I PGA Q DAC PGA ...
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... The cutoff frequency of the filters is programmable with the FIF[3:0] bits in register 04h, and should be set to the recommended settings detailed in the register description. PLL must be Rev. 1.0 Si4205 N [15: PLL PDIB 2 BBG[1:0] ...
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... GSM 850 and E-GSM 900 bands. For φ transmit mode, the RF2 and IF PLL phase detector update rates are always f =200 kHz. φ 65, 130 DET Self Tune RF PLL IF PLL Self Tune DET , N and RF1 RF2 Rev. 1.0 Aero I Si4205 RF1 To RX/TX RF2 N [15:0] RF1 N [15:0] RF2 [15: ...
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... The XOUT buffer is a CMOS driver stage with approximately 250 Ω of series resistance. This buffer is enabled when the XEN hardware control (pin 26 on the Si4205) is set high, independent of the PDN control pin. Last bit clocked in To achieve complete powerdown during sleep, the XEN ...
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Control Registers Reg Name D17 D16 D15 D14 D13 D12 D11 D10 01h Reset 02h Mode 03h Config 04h Transmit 05h Receive 11h Config 0 ...
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Aero I Register 01h. Reset Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:1 Reserved 0 RESET Register 02h. Mode Control Bit D17 D16 D15 D14 D13 D12 D11 D10 ...
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Register 03h. Configuration Bit D17 D16 D15 D14 D13 D12 D11 D10 Name DIAG[1:0] Bit Name 17:14 Reserved 13:12 DIAG[1:0] 11 SWAP 10:8 Reserved 7:6 TXBAND[1:0] 5:4 RXBAND[1:0] 3:2 Reserved 1 Reserved 0 Reserved D9 D8 ...
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Aero I Register 04h. Transmit Control Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:11 Reserved 10 Reserved 9:8 BBG[1:0] 7:4 FIF[3:0] 3:0 Reserved ...
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Register 05h. Receive Gain Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:14 Reserved 13:8 DGAIN[5:0] 7 Reserved 6:4 AGAIN[2:0] 3:2 LNAC[1:0] 1:0 LNAG[1: DGAIN[5:0] 0 Function Program ...
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Aero I Register 11h. Configuration Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:14 Reserved 13:11 DPDS[2:0] 10 XPD1 9 Reserved 8 XSEL 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3:1 ...
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... Reserved Note: DAC input is forced to zero after PDN is deasserted. This feature can be used by the baseband processor to cancel the Si4205 DAC dc offset. Offsets induced on channels due to 13 MHz harmonics will not be included in the calibrated value. RX Output Common Mode Voltage 1.0 V. ...
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Aero I Register 19h. Reserved Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:0 Reserved Register 20h. RX Master #1 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name RXBAND[1:0] ...
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Register 23h. TX Master #1 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name TXBAND[1:0] Notes: 1. See registers 03h and 34h for bit definitions. 2. When this register is written, the PDIB bit is automatically set to 1, ...
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Aero I Register 31h. Main Configuration Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name SDOSEL[3:0] Bit Name 17:15 Reserved 14:11 SDOSEL[3:0] 10:5 Reserved 4 RFUP 3 DIV2 2:1 Reserved 0 Reserved ...
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Register 32h. Powerdown Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Register 33h. RF1 N Divider Bit D17 D16 D15 D14 D13 D12 D11 ...
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Aero I Register 35h Divider Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name 17:16 Reserved Program to zero. 15:0 N [15:0] N Divider for IF Synthesizer. IF Used for transmit mode. ...
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... Pin Descriptions: Si4205-BM Pin Number(s) Name 1, 28 RXQN, RXQP 2, 3 RXIP, RXIN 4, 5 TXIP, TXIN 6, 7 TXQP, TXQN 8 XIN 9, 32 VDD 10 PDN 11 SDO 12 SEN 13 SCLK 14 SDI 15, 29–31 GND 16, 17 RFIPP, RFIPN 18, 19 RFIDP, RFIDN 20, 21 RFIGP, RFIGN 22 RFOD 23 RFOG 24, 25 ...
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... Aero I Ordering Guide Part Number Description Si4205-BM Tri-band Transceiver GSM 850 or E-GSM 900, DCS 1800, PCS 1900 Note: Add an “R” at the end of the part number to denote tape and reel option; 2500 quantity per reel. 34 Temperature – °C Rev. 1.0 Operating ...
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... Package Outline: Si4205-BM Figure 13. 32-Pin Land Grid Array (LGA) Notes: 1. Dimensions in mm. 2. Approximate device weight is 196 mg. Rev. 1.0 Aero I 35 ...
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... Added SEN programming option. Table 5 on page 8 updated. Updated 20 MHz GSM band desensitization specification. Updated Voltage Gain specification. "Bill of Materials‚" on page 15 updated. "Ordering Guide‚" on page 34 updated. "Package Outline: Si4205-BM‚" on page 35 updated. Added Note 1. Rev. 1.0 Aero I 36 ...
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Notes: Rev. 1.0 Aero I 37 ...
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