SI4021-A1-FT Silicon Laboratories Inc, SI4021-A1-FT Datasheet - Page 12

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SI4021-A1-FT

Manufacturer Part Number
SI4021-A1-FT
Description
IC TX FSK 915MHZ 5.4V 16-TSSOP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI4021-A1-FT

Package / Case
16-TSSOP
Frequency
433MHz, 868MHz, 915MHz
Modulation Or Protocol
FSK, OOK
Data Rate - Maximum
512kbps
Power - Output
8dBm
Current - Transmitting
24mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
2.2 V ~ 5.4 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
433 MHz to 915 MHz
Mounting Style
SMD/SMT
Operating Supply Voltage
2.2 V to 5.4 V
Supply Current
1.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Applications
-
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1622-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI4021-A1-FTR
Manufacturer:
SILICON
Quantity:
5 000
CONTROL INTERFACE
Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK
whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer
multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first
(e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default
values in all control and command registers.
The status information or received data can be read serially over the IRQ pin. Bits are shifted out upon the falling edge of CLK signal
Timing Specification
Timing Diagram
nSEL
nIRQ
SCK
SDI
Symbol
t
t
t
t
t
t
t
t
t
SHI
CH
DS
DH
OD
CL
SS
SH
BL
t
SS
t
DS
BIT15
t
DH
t
CH
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
Push-button input low time
t
CL
BIT14
BIT13
BIT8
t
OD
POR
BIT7
BIT1
WK-UP
BIT0
nIRQ
t
SH
Minimum value [ns]
t
SHI
25
25
10
10
25
10
25
5
5
Si4021
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