SI4010-C2-GT Silicon Laboratories Inc, SI4010-C2-GT Datasheet - Page 135

IC TX 27-960MHZ FSK 3.6V 10MSOP

SI4010-C2-GT

Manufacturer Part Number
SI4010-C2-GT
Description
IC TX 27-960MHZ FSK 3.6V 10MSOP
Manufacturer
Silicon Laboratories Inc
Series
EZRadio®r
Type
Crystalless SoC RF Transmitterr
Datasheet

Specifications of SI4010-C2-GT

Package / Case
10-MSOP
Mfg Application Notes
SI4010 Calculator Spreadsheet AppNote
Frequency
27MHz ~ 960MHz
Applications
Garage Openers, RKE, Security Alarms
Modulation Or Protocol
FSK, OOK
Data Rate - Maximum
100 kBaud
Power - Output
10dBm
Current - Transmitting
19.8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
4kB RAM
Features
8051 MCU Core, Crystal-less Operation
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
27 MHz to 960 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V to 3.6 V
Supply Current
14.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1997-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI4010-C2-GT
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
SI4010-C2-GT
Quantity:
100
Part Number:
SI4010-C2-GTR
Manufacturer:
ST
Quantity:
1 000
Part Number:
SI4010-C2-GTR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
SI4010-C2-GTR
0
Company:
Part Number:
SI4010-C2-GTR
Quantity:
10 000
34.5. 8-Bit Capture/Capture Mode (Split Mode)
When TMR2SPLIT=1, TMR2L_CAP=1 and TMR2H_CAP=1, both halves operate independently in 8-bit
capture modes. However, the capture event is the same for both timers. The clock sources for each timer
are selected independently, so one timer can capture short pulses while the other one long pulses, for
example.
Each 8-bit timer is free running, counts up and overflows from 0xFF to 0x00. Each time a capture event is
received, the contents of the timer registers (TMR2H and TMR2L) are latched into the corresponding timer
reload registers (TMR2RH and TMR2RL). Common capture event INT0 (INT1 for Timer 3) sets both high
and low half interrupt flags TMR2INTH and TMR2INTL at the same time.
The capture event can also generate its own external interrupt on top of the timer interrupt, if enabled by
the application. If the capture timer is stopped (TMR2L_RUN=0), the capture event still captures the cur-
rent counter register TMR2L into the reload register TMR2RL and sets the flag TRM2INTL. Same indepen-
dently applies to the upper half TMR2H with its respective registers and flags.
rtc_pulse (100us)
rtc_tick (5.33us)
clk_sys/12
clk_sys
Figure 34.4. Two 8-bit Timers in Timer/Timer Configuration (Split Mode)
TMR_CLKSEL
0
1
2
3
2
0
1
2
3
2
TMR2H_RUN
TMR2L_RUN
TMR2RH
TMR2RL
Rev. 1.0
TMR2H
TMR2L
Reload
Reload
TMR2INTH
TMR2INTL
TMR2INTL_EN
TMR2SPLIT
TMR2H_CAP
TMR2L_CAP
TMR2H_RUN
TMR2L_RUN
Si4010-C2
Interrupt
135

Related parts for SI4010-C2-GT