PK20N512VLK100 Freescale Semiconductor, PK20N512VLK100 Datasheet
PK20N512VLK100
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PK20N512VLK100 Summary of contents
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... Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2010–2011 Freescale Semiconductor, Inc. Preliminary Document Number: K20P81M100SF2 Rev. 4, 3/2011 K20P81M100SF2 • ...
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... UART switching specifications............................53 6.8.9 SDHC specifications...........................................53 6.8.10 I2S switching specifications................................54 6.9 Human-machine interfaces (HMI)......................................56 6.9.1 TSI electrical specifications................................56 7 Dimensions...............................................................................57 7.1 Obtaining package dimensions.........................................57 8 Pinout........................................................................................58 8.1 K20 Signal Multiplexing and Pin Assignments..................58 8.2 K20 Pinouts.......................................................................62 9 Revision History........................................................................63 Preliminary Freescale Semiconductor, Inc. ...
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... Field Q Qualification status K## Kinetis family M Flash memory type K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. http://www.freescale.com Description • Fully qualified, general market flow • Prequalification • K20 • Program flash only • Program flash and FlexMemory Table continues on the next page ...
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... MC = 121 MAPBGA ( mm) • 144 LQFP ( mm) • 144 MAPBGA ( mm) • 196 MAPBGA ( mm) • 256 MAPBGA ( mm) • MHz • MHz • 100 = 100 MHz • 120 = 120 MHz • 150 = 150 MHz • Tape and reel • (Blank) = Trays Preliminary Values Freescale Semiconductor, Inc. ...
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... Example This is an example of an attribute: Symbol Description CIN_D Input capacitance: digital pins K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Max. 0.9 1.1 Min. Max. 10 130 Min. ...
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... Result of exceeding a rating Measured characteristic K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 6 Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating Preliminary Max. Unit V Freescale Semiconductor, Inc. ...
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... Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Normal Limited operating operating range ...
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... Ambient temperature A V 3.3 V supply voltage DD 4 Ratings K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 8 Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Preliminary Max. Unit 130 µ 150 °C 105 °C 25 °C –40 °C Unit °C V Freescale Semiconductor, Inc. ...
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... Description V Digital supply voltage DD I Digital supply current DD V Digital input voltage (except RESET, EXTAL, and XTAL) DIO K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. –55 — — Min. — Min. -2000 -500 -100 Table continues on the next page... ...
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... V DD Table continues on the next page... Preliminary Min. Max. Unit –0 0 – – –0.3 3.63 V –0.3 3.63 V –0.3 6.0 V –0.3 3.8 V Max. Unit Notes 3.6 V 3.6 V 0.1 V 0.1 V 3.6 V — V — V 0.35 × 0.3 × — V Freescale Semiconductor, Inc. ...
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... V Bandgap voltage reference BG t Internal low power oscillator period LPO factory trimmed K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min 1.2 TBD , and induce an injection current when V SS supply LVD and POR operating requirements Min. ...
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... DD SS min and Vinput = and VLLSx→RUN recovery times in the following table Preliminary Typ. Max. Unit Notes 1.1 TBD V Max. Unit Notes — V — V — V — V 100 mA 0.5 V 0.5 V 0.5 V 0.5 V 100 mA 1 μ μA 50 kΩ kΩ 3 Freescale Semiconductor, Inc. ...
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... VLPS → RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.1.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol Description I Analog supply current DDA K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. — DD — — — — — — ...
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... TBD — 35 TBD — 15 TBD — 0.4 TBD — 1.25 TBD — TBD TBD — 1.05 TBD — 50 TBD — 12 TBD — 8 TBD — 4 TBD — 2 TBD — 550 TBD Preliminary Unit Notes μA μA μA μA μ Freescale Semiconductor, Inc. ...
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... Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled The following data was measured under these conditions: • MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary General 15 ...
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... Radiated emissions voltage, band 4 RE4 V IEC and SAE level RE_IEC_SAE K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 16 Frequency Typ. band (MHz) 0.15–50 TBD 50–150 TBD 150–500 TBD 500–1000 TBD 0.15–1000 TBD Preliminary Unit Notes dBμ — Freescale Semiconductor, Inc. ...
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... Bus clock BUS FB_CLK FlexBus clock f Flash clock FLASH f System and core clock SYS K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc MHz SYS Table 8. Capacitance attributes Min. Normal run mode — 20 — — — VLPR mode — ...
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... K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 18 Min. Max. — 2 — 2 — 1 Min. Max. 1.5 — 100 — 16 — TBD — 2 — — 12 — 36 — 32 — 36 Preliminary Unit Notes MHz MHz MHz Unit Notes Bus clock 1 cycles Bus clock cycles Freescale Semiconductor, Inc. ...
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... Core modules K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. –40 –40 81 ...
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... JTAG and CJTAG • Serial Wire Debug K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 20 Frequency dependent Ts Th Table continues on the next page... Preliminary Min. Max. Unit MHz 2 — — ns — — — — Min. Max. Unit 2.7 3.6 V MHz Freescale Semiconductor, Inc. ...
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... Boundary scan input data hold time after TCLK rise J7 TCLK low to boundary scan output data valid J8 TCLK low to boundary scan output high-Z K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table continues on the next page... Preliminary Min. Max. ...
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... Figure 6. Boundary scan (JTAG) timing K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 Figure 5. Test clock input timing Preliminary Min. Max. Unit 8 — ns 1.4 — ns — 22.1 ns — 22.1 ns 100 — — Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...
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... J13 TRST 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J11 J12 J11 Figure 7. Test Access Port timing J14 Figure 8 ...
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... TBD %f dco — 4 MHz — 5 MHz — µA TBD µs — — kHz — — kHz — 39.0625 kHz 25 MHz 2, 50 MHz 75 MHz 100 MHz Freescale Semiconductor, Inc ...
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... This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE crystal/resonator is being used as the reference, this specification assumes it is already running. K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — ...
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... Table continues on the next page... Preliminary Max. Unit Notes 3 — nA — μA — μA — μA — mA — — μA — μA — μA — mA — mA — mA — — — MΩ — MΩ — MΩ — MΩ Freescale Semiconductor, Inc. ...
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... Input clock frequency (external clock mode) ec_extal t Input clock duty cycle (external clock mode) dc_extal K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — — — — — ...
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... Min. Typ. 1.71 — — 100 — 2.5 — 15 — 0.6 Min. Typ. Max. — 32 — — 1000 — Preliminary Unit Notes Max. Unit 3.6 V — MΩ — pF — pF — V Unit Notes kHz ms 1 Freescale Semiconductor, Inc. ...
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... Read 1s All Blocks execution time rd1all t Read Once execution time rdonce t Program Once execution time pgmonce K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 20 — 20 — 160 Min. Typ. ...
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... Table continues on the next page... Preliminary Max. Unit Notes 1600 μs 1 Typ. Unit 10 mA Max. Unit Notes 1 — years 2 — years 2 — years 2 — cycles 3 Min. Max. Unit 2.7 3.6 V — MHz SYS — MHz SYS — ns EZP_CK 5 — — ns Freescale Semiconductor, Inc. ...
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... Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 23. Flexbus switching specifications Num Description Operating voltage Frequency of operation K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EP3 EP2 EP4 EP9 EP7 EP8 ...
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... Figure 10. FlexBus read timing diagram K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 32 (continued) Min. 20 TBD 0 8.5 0.5 FB3 FB5 Address FB4 Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ Preliminary Max. Unit Notes — — — — Freescale Semiconductor, Inc. ...
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... Figure 11. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB3 Address Data ...
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... Table continues on the next page... Preliminary are achievable on the Table 26 and Max. Unit Notes 3.6 V +100 mV 2 +100 DDA V V SSA V V REFH kΩ kΩ 4 18.0 MHz 5 12.0 MHz Freescale Semiconductor, Inc. ...
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... For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 7. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 Max. ...
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... CHANNEL SELECT CIRCUIT ADC SAR ENGINE R ADIN R ADIN R ADIN R ADIN C ADIN , REFL SSA 2 Max. Unit Notes 1 — MHz ADACK f ADACK — MHz — MHz — MHz ±TBD ADC 4 LSB conversion ±1 clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Freescale Semiconductor, Inc. ...
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... Avg=32 SFDR Spurious free 16 bit differential mode dynamic range • Avg=32 16 bit single-ended mode • Avg=32 K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = REFH DDA REFL 1 Min. Typ. ...
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... VREFOUT VREFOUT VREFOUT V — SSA V — SSA Table continues on the next page... Preliminary = V ) (continued) SSA 2 Max. Unit Notes leakage current (refer to the MCU's voltage and current operating ratings) — mV/°C — mV/°C — mV Max. Unit Notes 3 DDA V V DDA Freescale Semiconductor, Inc. ...
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... PGAG=5 • PGAG=6 BW Input signal • 16-bit modes bandwidth • < 16-bit modes PSRR Power supply Gain=1 rejection ration K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 Typ. — 128 — 64 — 32 — ...
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... DDA to 3.6V TBD %/ leakage AS In current (refer to the MCU's voltage and current operating ratings × 0.583 — dB 16-bit differential — dB mode, Average=32 — dB 16-bit differential — dB mode, Average=32, f =500Hz in — dB 16-bit differential — dB mode, Average=32, f =500Hz in Freescale Semiconductor, Inc. ...
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... I Supply current, low-speed mode (EN=1, PMODE=0) DDLS V Analog input voltage AIN V Analog input offset voltage AIO K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. TBD 12.3 TBD 12.7 TBD 8.4 TBD 8 ...
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... V – 0.5 DD — 20 120 — 2 — –0.5 –0.3 -0.6V. DD Preliminary Typ. Max. Unit 5 — — — — mV — — V — 0 200 ns 250 600 ns — TBD ns 7 — μA — 0.5 3 LSB — 0.3 LSB Freescale Semiconductor, Inc. ...
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... Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1.3 1.6 1.9 2.2 Vin level (V) Preliminary HYSTCTR S etting 00 ...
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... A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011 1.3 1.6 1.9 2.2 Vin level (V) Min. 1.71 1.13 −40 — — Preliminary HYSTCTR Setting 2.5 2.8 3.1 Max. Unit Notes 3 105 °C 100 Freescale Semiconductor, Inc. ...
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... LP 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV The DNL is measured for 0+100 The DNL is measured for 0+100mV to V K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — — ...
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... Peripheral operating requirements and behaviors 5. Calculated by a best fit curve from V Figure 17. Typical INL error vs. digital code K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 46 +100 mV to VREF−100 mV SS Preliminary Freescale Semiconductor, Inc. ...
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... Table 32. VREF full-range operating behaviors Symbol Description V Voltage reference output with factory trim at out nominal V and temperature=25C DDA K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1.71 −40 — Min. Typ. TBD 1.2 Table continues on the next page ...
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... Typ. Max. Unit Notes — TBD V — 1.202 V 0.5 — mV — See Figure 19 — TBD ppm/year — TBD µA — 1.1 mA — TBD V — 100 µs — TBD mV — TBD dB Max. Unit Notes 50 °C Max. Unit Notes TBD V Freescale Semiconductor, Inc. ...
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... Maximum load current — Standby mode LOADstby V Regulator output voltage — Input supply Reg33out (VREGIN) > 3.6 V • Run mode • Standby mode K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. TBD 0 14.25 0.25 Min ...
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... Min. Max. 1.71 3.6 — 12 — BCLK (t / SCK SCK/ — SCK (t / — SCK — — 15 — 0 — Preliminary Unit Notes V 1 μF mΩ Load Unit Notes V 1 MHz Freescale Semiconductor, Inc. ...
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... DSPI_SS inactive to DSPI_SOUT not driven DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DS13 DSPI_SIN Figure 22. DSPI classic SPI timing — slave mode K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DS1 DS2 DS8 Data Last data First data DS5 ...
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... V — 25 MHz — ns BCLK (t /2) − / SCK SCK (t /2) − 2 — ns SCK (t /2) − 2 — ns SCK — 8.5 ns −2 — ns TBD — — ns DS4 Min. Max. Unit 2.7 3.6 V 12.5 MHz — ns BCLK (t /2) − SCK SCK Freescale Semiconductor, Inc. ...
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... C switching specifications See General switching specifications. 6.8.8 UART switching specifications See General switching specifications. K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Description DS10 DS15 DS12 First data Data DS14 First data ...
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... K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 54 Card input clock SD3 SD2 SD1 SD6 SD7 SD8 Figure 25. SDHC timing Preliminary Min. Max. Unit 2.7 3 400 kHz 0 25 MHz 0 20 MHz 0 400 kHz 7 — — ns — — 6 — — ns Freescale Semiconductor, Inc. ...
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... I2S_RXD/I2S_FS input hold after I2S_BCLK I2S_MCLK (output) I2S_BCLK (output I2S_FS (output) I2S_FS (input) S7 I2S_TXD I2S_RXD Figure 26. I K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors master (clocks driven) and slave 2 S master mode timing ...
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... Table continues on the next page... Preliminary Min. Max. Unit 2.7 3 — ns SYS 45% 55% MCLK period 10 — — ns — — — — ns S16 S14 S16 Typ. Max. Unit Notes — 3 500 pF 5.5 TBD MHz 0.5 TBD MHz Freescale Semiconductor, Inc. 1 ...
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... Package dimensions are provided in package drawings. To find a package drawing search for the drawing’s document number: If you want the drawing for this package 80-pin LQFP 81-pin MAPBGA K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Min. Typ. TBD 1 TBD 600 ...
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... NOTE ALT1 ALT2 ALT3 ALT4 PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 PTE1 SPI1_SOUT UART1_RX SDHC0_D0 PTE2 SPI1_SCK UART1_CT SDHC0_DC S_b LK PTE3 SPI1_SIN UART1_RT SDHC0_CM S_b D PTE4 SPI1_PCS0 UART3_TX SDHC0_D3 PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 Preliminary ALT5 ALT6 ALT7 EzPort I2C1_SDA I2C1_SCL Freescale Semiconductor, Inc. ...
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... VDD • 39 VSS VSS VSS • 40 PTA18 EXTAL EXTAL • 41 PTA19 XTAL XTAL K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA0 UART0_CT FTM0_CH5 S_b PTA1 UART0_RX FTM0_CH6 PTA2 UART0_TX FTM0_CH7 PTA3 UART0_RT FTM0_CH0 ...
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... SPI0_PCS1 UART1_RX FTM0_CH2 PTC4 SPI0_PCS0 UART1_TX FTM0_CH3 Preliminary ALT5 ALT6 ALT7 EzPort FTM1_QD_ PHA FTM1_QD_ PHB FTM0_FLT3 FTM0_FLT0 FB_AD19 FTM0_FLT1 FB_AD18 FTM0_FLT2 FB_AD17 EWM_IN FB_AD16 EWM_OUT _b FB_AD15 FTM2_QD_ PHA FB_OE_b FTM2_QD_ PHB FB_AD14 FB_AD13 FB_AD12 FB_CLKOU T FB_AD11 CMP1_OUT Freescale Semiconductor, Inc. ...
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... PTD6 / / ADC0_SE7 ADC0_SE7 b b • — VSS VSS VSS • 80 PTD7 K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTC5 SPI0_SCK LPT0_ALT2 FB_AD10 PTC6 SPI0_SOUT PDB0_EXT RG PTC7 SPI0_SIN PTC8 I2S0_MCLK I2S0_CLKIN FB_AD7 PTC9 I2S0_RX_B ...
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... The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. The 81 MAPBGA ballmap assignments are currently being developed. K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 62 NOTE Preliminary Freescale Semiconductor, Inc. ...
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... PGA1_DM/ADC1_DM0/ADC0_DM3 17 VDDA 18 VREFH 19 VREFL 20 VSSA Figure 28. K20 80 LQFP Pinout Diagram 9 Revision History The following table provides a revision history for this document. K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary Revision History 60 VDD 59 VSS 58 PTC3 57 PTC2 56 PTC1 55 PTC0 ...
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... Corrected 81- and 104-pin package codes Added sections that were inadvertently removed in previous revision Reworded I footnote in "Voltage and Current Operating Requirements" IC table. Added paragraph to "Peripheral operating requirements and behaviors" section. Added "JTAG full voltage range electricals" table to the "JTAG electricals" section. Preliminary Freescale Semiconductor, Inc. ...
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... Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time ...