PK30N512VLK100 Freescale Semiconductor, PK30N512VLK100 Datasheet - Page 30

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PK30N512VLK100

Manufacturer Part Number
PK30N512VLK100
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheet

Specifications of PK30N512VLK100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, I²C, IrDA, SDHC, SPI, UART/USART
Peripherals
DMA, I²S, LCD, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 27x16b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PK30N512VLK100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral operating requirements and behaviors
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash (FTFL) current and power specfications
6.4.1.4 Reliability specifications
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
2. Data retention is based on T
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ T
6.4.2 EzPort Switching Specifications
30
t
t
t
nvmretp10k
nvmretp100
n
Symbol
Symbol
nvmretp1k
t
nvmcycp
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
t
vfykey
ersall
EP1a
Num
EP1
EP2
EP3
EP4
I
Symbol
DD_PGM
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Data retention after up to 10 K cycles
Data retention after up to 1 K cycles
Data retention after up to 100 cycles
Cycling endurance
Description
Description
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
Description
Table 19. Flash command timing specifications (continued)
Worst case programming current in program flash
Description
Table 20. Flash (FTFL) current and power specfications
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
javg
Table 22. EzPort switching specifications
Table 21. NVM reliability specifications
= 55°C (temperature profile over the lifetime of the application).
Table continues on the next page...
Program Flash
Preliminary
10 K
Min.
Min.
10
15
5
Typ.
j
TBD
TBD
TBD
TBD
Typ.
320
≤ 125°C.
2 x t
1
Min.
2.7
EZP_CK
5
5
1600
Max.
Max.
Typ.
35
10
Freescale Semiconductor, Inc.
f
f
Max.
SYS
SYS
3.6
/2
/8
cycles
years
years
years
Unit
Unit
ms
μs
Unit
mA
MHz
MHz
Unit
Notes
Notes
ns
ns
ns
V
2
1
2
2
2
3

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