PK30N512VLK100 Freescale Semiconductor, PK30N512VLK100 Datasheet - Page 36

• Manufacturer Part Number: PK30N512VLK100
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK30N512VLK100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, I²C, IrDA, SDHC, SPI, UART/USART
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 27x16b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Peripheral operating requirements and behaviors
FIGURE TBD
6.6.1.3 16-bit ADC with PGA operating conditions
1. Typical values assume V
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (R
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
6.6.1.4 16-bit ADC with PGA characteristics
36
V
I
Symbol
Symbol
I
DDA_PGA
R
Figure 12. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended
DC_PGA
REFPGA
V
V
reference only and are not tested in production.
of the VREF module, the VREF module must be disabled.
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
time should be allowed for F
8 MHz ADC clock.
V
R
I
PGAD
ADIN
T
ILKG
DDA
CM
AS
S
Supply voltage
PGA ref voltage
Input voltage
Input Common
Mode range
Differntial input
impedance
Analog source
resistance
ADC sampling
time
Description
Supply current
Input DC current
Input Leakage
current
Description
Table 25. 16-bit ADC with PGA operating conditions
DDA
Table 26. 16-bit ADC with PGA characteristics
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
in
Absolute
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
Conditions
= 3.0 V, Temp = 25°C, f
=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
PGA disabled
Conditions
AS
), external to MCU, should be kept as minimum as possible. Increased R
Table continues on the next page...
Preliminary
ADCK
VREFOUT VREFOUT VREFOUT
modes
V
V
1.71
1.25
Min.
—
—
—
—
= 6 MHz unless otherwise stated. Typical values are for
SSA
SSA
Min.
—
—
Typ.
128
100
64
32
—
—
—
—
1
Typ.
TBD
590
1
V
V
Max.
3.6
—
—
—
—
—
DDA
DDA
Max.
TBD
TBD
Freescale Semiconductor, Inc.
Unit
kΩ
µs
V
V
V
V
Ω
Unit
μA
μA
A
AS
IN+ to IN-
causes drop
Notes
Notes
2,
5
6
2
3
3
4