WJLXT972ALC.A4-857345 Cortina Systems Inc, WJLXT972ALC.A4-857345 Datasheet - Page 40

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WJLXT972ALC.A4-857345

Manufacturer Part Number
WJLXT972ALC.A4-857345
Description
TXRX ETH 10/100 SGL PORT 64-LQFP
Manufacturer
Cortina Systems Inc

Specifications of WJLXT972ALC.A4-857345

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
1008-1043-2

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Quantity
Price
Part Number:
WJLXT972ALC.A4-857345
Manufacturer:
Cortina
Quantity:
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Part Number:
WJLXT972ALC.A4-857345
Manufacturer:
Cortina Systems Inc
Quantity:
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LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Table 15
5.7.3.2
5.7.3.2.1
5.7.3.2.2
Note:
Caution:
Cortina Systems
4B/5B Coding (Sheet 2 of 2)
Physical Medium Attachment Sublayer
Link
In 100 Mbps mode, link is established when the descrambler becomes locked and
remains locked for approximately 50 ms. Link remains up unless the descrambler
receives less than 16 consecutive idle symbols in any 2 ms period. This operation filters
out small noise hits that may disrupt the link.
For short periods, MLT-3 idle waveforms meet all criteria for 10BASE-T start delimiters. A
working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms.
However, the PHY does not bring up a permanent 10 Mbps link.
The LXT972A PHY reports link failure through the MII status bits (register bits 1.2 and
17.10) and interrupt functions. Link failure causes the LXT972A PHY to re-negotiate if
auto-negotiation is enabled.
Link Failure Override
The LXT972A PHY normally transmits data packets only if it detects the link is up. Setting
register bit 16.14 = 1 overrides this function, allowing the LXT972A PHY to transmit data
packets even when the link is down. This feature is provided as a transmit diagnostic tool.
Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-
negotiation is enabled, the LXT972A PHY automatically transmits FLP bursts if the link is
down.
During normal operation, Cortina does not recommend setting register bit 16.14 for
100 Mbps receive functions because receive errors may be generated.
®
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
Code Type
LXT972A Single-Port 10/100 Mbps PHY Transceiver
INVALID
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
4B Code
3 2 1 0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Name
H
4
4 3 2 1 0
5B Code
0 0 1 0 0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 1 0 0 1
Transmit Error. Used to force signaling
errors
Interpretation
5.7 100 Mbps Operation
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Page 40

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