S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 109

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
21.1.2 S1D13743 Register Settings for 352x416 TFT Panel
Hardware Functional Specification
Issue Date: 2010/05/18
REG[04h] bit 7
REG[0Ah]
REG[0Ch]
REG[0Eh]
REG[1Ah]
REG[1Ch]
REG[1Eh]
REG[2Ah]
REG[3Ah]
REG[3Ch]
REG[3Eh]
REG[56h]
REG[04h]
REG[06h]
REG[08h]
REG[12h]
REG[14h]
REG[16h]
REG[18h]
REG[20h]
REG[22h]
REG[24h]
REG[26h]
REG[28h]
REG[56h]
REG[38h]
REG[40h]
REG[42h]
Register
All
Note
Note
Table 21-2: Example Register Settings for 352x416 TFT Panel
The registers listed below are only those associated with panel specific timing issues All
other registers are not shown here.
When a window is setup for YUV data, the data must always alternate between odd and
even lines, starting with an odd line.
default
Value
2Ch
2Dh
12h
F8h
80h
28h
00h
2Fh
19h
5Ah
A0h
01h
06h
14h
02h
01h
80h
00h
00h
00h
00h
00h
5Fh
01h
02h
01h
0h
—
Come out of reset - all registers set to default values
enter sleep mode (or use PWRSVE pin)
set PLL M-Divider.
CLKI = 19.2MHz,
PLL input clock = CLKI/19 = 1.01MHz.
LL = 48, resulting SYSCLK = LL x PLL input clock = 48MHz
set PCLK divide, PCLK = 12.1MHz
set SYSCLK source = PLL
no panel data swap, 18-bit panel
HDP = 352 pixels
HNDP = 90 pixels
VDP = 416 lines
VNDP = 6 lines
HS Pulse Width = 20 pixels
HS Start Position = 45 pixels
VS Width = 2 lines
VS Start Position (VFP) = 1 line
PCLK Polarity: data output on falling edge
set input data mode to RGB 5:6:5
disable sleep mode
wait for PLL to lock - poll REG[04h] bit 7
Window X Start Position = 0
Window Y Start Position = 0
Window X End Position = 351
Revision 2.7
Comment
X70A-A-001-02
S1D13743
Page 109