S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 54
S1D13743F00A200
Manufacturer Part Number
S1D13743F00A200
Description
LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
Manufacturer
Epson
Datasheet
1.S1D13743F00A200.pdf
(134 pages)
Specifications of S1D13743F00A200
Maximum Clock Frequency
33 MHz, 68.59 MHz
Operating Supply Voltage
1.5 V
Maximum Operating Temperature
+ 85 C
Package / Case
QFP-20-144
Attached Touch Screen
No
Maximum Supply Current
74 mA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S1D13743F00A200
Manufacturer:
EPSON
Quantity:
5 690
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S1D13743
X70A-A-001-02
bits 6-0
bit 7
bits 5-0
bits 7-0
bit 7
REG[22h] HS Pulse Start Position Register (HPS)
Default = 00h
REG[24h] VS Pulse Width Register (VSW)
Default = 00h
REG[26h] VS Pulse Start Position Register (VPS)
Default = 00h
REG[28h] PCLK Polarity Register
Default = 00h
VS Pulse Polarity
PCLK Polarity
n/a
7
7
7
7
n/a
6
6
6
6
HS Pulse Start Position bits [6:0]
These bits specify the start position of the horizontal sync signal with respect to the start of
Horizontal Non-Display period (HPS), in pixels.
VS Pulse Polarity
This bit selects the polarity of the vertical sync signal. This bit is set according to the ver-
tical sync signal of the panel.
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
VS Pulse Width bits [5:0]
These bits specify the width of vertical sync signal for the panel (VSW), in lines. The ver-
tical sync signal is typically VS, depending on the panel type.
VS Pulse Start Position bits [7:0]
These bits specify the start position of the vertical sync signal with respect to the start of
Vertical Non-Display period (VPS), in lines.
PCLK Polarity
This bit selects the polarity of PCLK.
When this bit = 0, data is output on the rising edge of PCLK.
When this bit = 1, data is output on the falling edge of PCLK.
HPS in pixels = REG[22h] bits 6-0
VSW in lines = REG[24h] bits 5-0
VPS in lines = REG[26h] bits 7-0
5
5
5
5
VS Pulse Start Position bits 7-0
4
4
4
4
Revision 2.7
HS Pulse Start Position bits 6-0
VS Pulse Width bits 5-0
n/a
3
3
3
3
2
2
2
2
Epson Research and Development
Hardware Functional Specification
1
1
1
1
Vancouver Design Center
Issue Date: 2010/05/18
Read/Write
Read/Write
Read/Write
Read/Write
0
0
0
0
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