S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 99

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
19 Host Interface
19.1 Using the Intel 80 Interface
Hardware Functional Specification
Issue Date: 2010/05/18
Note
Accessing the S1D13743 through the Intel 80 host interface is a multiple step process. All
Registers and Memory are accessed through the register space.
First, perform a single “Address Write” to setup the register address. Next, perform a “Data
Read/Write” to specify the data to be stored or read from the registers or memory specified
in the “Address Write” cycle. Subsequent data read/writes without an Address Write to
change the register address, will automatically “auto” increment the register address, or the
internal memory address if accessing the Memory Data Port (REG[48h], REG[49h]).
To write display data to a Window Aperture, specify the Window coordinates followed by
burst data writes to the Memory Data Port to fill the window. In this sequence, the internal
memory addressing is automatic (see examples). The Memory Data Port is located directly
following the Window coordinates to minimize the number of Address Writes.
To read display data, perform an Address Write to the Memory Address Port (3 bytes) and
then read data from the Memory Data Port. Sequential reads will auto-increment the
internal memory address
All Register accesses are 8-bit only, except for the Memory Data Port. If the Host
interface is 16-bits wide (CNF1 = 1b), the lsbs (MD[7:0]) are used for all registers
except the Memory Data Port.
For the Memory Data Port (REG[48h, 49h]), both registers are used when the host
interface is 16-bits wide (CNF1 = 1b) and only REG[48h] is used when it is 8-bits
wide (CNF1 = 0b).
Revision 2.7
X70A-A-001-02
S1D13743
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