AGLP-EVAL-KIT Actel, AGLP-EVAL-KIT Datasheet - Page 31

MCU, MPU & DSP Development Tools IGLOO PLUS Starter Kit

AGLP-EVAL-KIT

Manufacturer Part Number
AGLP-EVAL-KIT
Description
MCU, MPU & DSP Development Tools IGLOO PLUS Starter Kit
Manufacturer
Actel
Datasheet

Specifications of AGLP-EVAL-KIT

Processor To Be Evaluated
CSG289
Interface Type
USB, JTAG
Operating Supply Voltage
1.2 V to 1.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Flash*Freeze Types
IGLOO PLUS Starter Kit User’s Guide
Type 1: Control by dedicated Flash*Freeze Pin.
Type 2: Control by dedicated Flash*Freeze Pin and Internal Logic.
Flash*Freeze Type 1: Control by Dedicated Flash*Freeze Pin
Flash*Freeze type 1 is intended for systems where either the device will be reset upon exiting Flash*Freeze mode, or data
and clock are managed externally. The device enters Flash*Freeze mode 1 μs after the dedicated FF pin is asserted (active
low), and returns to normal operation when the FF pin is deasserted (high). In this mode, FF pin assertion or
deassertion is the only condition that determines entering or exiting Flash*Freeze mode
O buffer macro must be used to identify the Flash*Freeze input in your design.
Flash*Freeze Pin
Mode Control
Flash*Freeze
Figure 4-4 · Flash*Freeze Mode Type 1 – Controlled by the Flash*Freeze Pin
Flash*Freeze (FF) Pin
Figure 4-5 · Flash*Freeze Mode Type 1 – Timing Diagram
Operation
Normal
Flash*Freeze
INBUF_FF
t = 1 µs
Signal
Actel IGLOO, IGLOO PLUS, IGLOO nano,
Flash*Freeze
Flash*Freeze
Technology
Mode
To FPGA Core or Floating
ProASIC3L, or RT ProASIC3 Device
AND
Enables Entering
Flash*Freeze Mode
Flash*Freeze
Mode
1
t = 1 µs
(Figure
User Design
4-4). An INBUF_FF I/
Flash*Freeze Mode
Operation
Normal
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