WM9090ECS/R Wolfson Microelectronics, WM9090ECS/R Datasheet - Page 70

• Manufacturer Part Number: WM9090ECS/R
• Description: Audio CODECs Audio Subsystem w/ capless headphones
• Manufacturer: Wolfson Microelectronics

Specifications of WM9090ECS/R

• Interface Type: 2-Wire, l2C
• Thd Plus Noise: 80 dB
• Ic Function: Ultra Low Power Audio Subsystem
• Brief Features: Mono Class D Speaker Driver, Automatic Gain Control (AGC)
• Supply Voltage Range: 2.7V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM9090
w
Register 58h DC Servo Readback 0
Register 59h DC Servo Readback 1
Register 5Ah DC Servo Readback 2
Readback 1
Readback 2
REGISTER
REGISTER
REGISTER
REGISTER
ADDRESS
ADDRESS
ADDRESS
ADDRESS
R90 (5Ah)
R89 (59h)
R96 (60h)
DC Servo
DC Servo
Analogue
HP 0
BIT
BIT
BIT
BIT
5:4
1:0
7:0
7:0
7
6
5
R_COMPLETE
DCS_STARTU
P_COMPLETE
HPOUT1L_RM
HPOUT1L_OU
HPOUT1L_DL
DCS_DAC_W
DCS_DAC_W
R_VAL_1_RD
DCS_DAC_W
R_VAL_0_RD
V_SHORT
LABEL
LABEL
LABEL
LABEL
[1:0]
[1:0]
[7:0]
[7:0]
TP
Y
0000_0000 Readback value for HPOUT1R.
0000_0000 Readback value for HPOUT1L.
DEFAULT
DEFAULT
DEFAULT
DEFAULT
00
00
0
0
0
DC Servo DAC Write status
0 = DAC Write DC Servo mode not completed.
1 = DAC Write DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
DC Servo Start-Up status
0 = Start-Up DC Servo mode not completed.
1 = Start-Up DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Removes HPOUT1L short
0 = HPOUT1L short enabled
1 = HPOUT1L short removed
For pop-free operation, this bit should be set to 1 as the
final step in the HPOUTL Enable sequence.
Enables HPOUT1L output stage
0 = Disabled
1 = Enabled
For pop-free operation, this bit should be set to 1 after
the DC offset cancellation has been performed.
Enables HPOUT1L intermediate stage
0 = Disabled
1 = Enabled
For pop-free operation, this bit should be set to 1 after
the output signal path has been configured, and before
the DC Offset cancellation is scheduled This bit should
be set with at least 20us delay after HPOUT1L_ENA.
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
PD, November 2010, Rev 4.1
REFER TO
REFER TO
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REFER TO
Production Data
70