AGLN010V2-QNG48 Actel, AGLN010V2-QNG48 Datasheet - Page 49
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AGLN010V2-QNG48
Manufacturer Part Number
AGLN010V2-QNG48
Description
FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN010V2-QNG48
Processor Series
AGLN010
Core
IP Core
Number Of Macrocells
86
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
34
Supply Voltage (max)
1.5 V
Supply Current
3 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
10 K
Package / Case
QFN-48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLN010V2-QNG48I
Manufacturer:
ACTEL10
Quantity:
4 142
Table 2-51 • Minimum and Maximum DC Input and Output Levels
Figure 2-9 • AC Loading
Table 2-52 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
1.8 V
LVCMOS
Drive
Strength
2 mA
4 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input LOW (V)
0
*
Measuring point = Vtrip. See
current is larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
Min.
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
V
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Test Point
Datapath
VIL
Max.
V
Table 2-23 on page 2-20
5 pF
Min.
Input HIGH (V)
V
VIH
1.8
Max.
Enable Path
3.6
3.6
Test Point
V
R = 1 k
Max.
VOL
0.45
0.45
V
for a complete table of trip points.
R ev i si o n 1 1
VCCI – 0.45
VCCI – 0.45
Measuring Point* (V)
VOH
Min.
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
V
0.9
mA mA
I
OL
2
4
HZ
ZH
I
OH
/ t
2
4
/ t
IGLOO nano Low Power Flash FPGAs
LZ
LZ
HZ
ZHS
/ t
/ t
Max.
mA
I
OSL
17
ZL
/ t
9
ZH
3
/ t
ZL
/ t
ZLS
/ t
ZHS
ZLS
C
LOAD
Max.
I
mA
OSH
22
11
5
3
(pF)
µA
I
IL
10
10
1
4
I
µA
2- 35
IH
10
10
2
4