LFXP3C-5TN100C Lattice, LFXP3C-5TN100C Datasheet - Page 97
![FPGA - Field Programmable Gate Array 3.1K LUTS 62 I/O](/photos/16/2/160258/tqfp-100_sml.jpg)
LFXP3C-5TN100C
Manufacturer Part Number
LFXP3C-5TN100C
Description
FPGA - Field Programmable Gate Array 3.1K LUTS 62 I/O
Manufacturer
Lattice
Specifications of LFXP3C-5TN100C
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
Number
M21
M22
Ball
K22
K21
K20
H22
H21
K19
H20
H19
G19
G22
G21
G20
E22
E21
D22
D21
E20
D20
D19
D18
E19
D17
D16
C16
C15
C17
C18
C19
L22
L19
L20
L21
J22
J21
J19
J20
F20
F22
F21
F19
-
-
-
-
-
-
-
Function
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO1
GNDIO1
VCCP1
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PT39A
PT38B
PR9B
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR5A
PR4B
PR4A
PR3B
PR3A
PR2B
PR2A
VCCJ
TDO
TMS
TCK
Ball
TDI
-
-
-
-
-
-
Bank Diff.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
LFXP10
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
Dual Function
PCLKC2_0
PCLKT2_0
VREF1_2
VREF2_2
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Function
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO1
GNDIO1
VCCP1
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR10B
PT48A
PT47B
PT47A
PT46B
PT45A
PT44B
PT44A
PT43B
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
VCCJ
TDO
TMS
TCK
Ball
TDI
Bank Diff.
4-38
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
-
LFXP15
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
Dual Function
PCLKC2_0
PCLKT2_0
VREF1_2
VREF2_2
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeXP Family Data Sheet
Function
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO1
GNDIO1
VCCP1
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR10B
PT52A
PT51B
PT51A
PT50B
PT49A
PT48B
PT48A
PT47B
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
VCCJ
TDO
TMS
TCK
Ball
TDI
Bank Diff.
Pinout Information
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
LFXP20
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
C
C
C
C
C
C
C
T
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RUM0_PLLC_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_FB_A
RUM0_PLLT_IN_A
Dual Function
PCLKC2_0
PCLKT2_0
VREF1_2
VREF2_2
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-