LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 293
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Wake Up Options
When configuration is complete (the SRAM has been loaded), the device should wake up in a predictable fashion.
The following selections determine how the device will wake up. Two synchronous wake up processes are avail-
able. One automatically wakes the device up when the internal Done bit is set regardless of whether the DONE pin
is held low externally or not, the other waits for the DONE pin to be driven high before starting the wake up process.
The DONE_EX preference determines whether the external DONE pin will control the synchronous wake up. When
the device is in the SDM mode the DONE pin is not used and therefore the DONE_EX preference has no effect.
Wake Up Sequence
Table 14-6 provides a list of the wake up sequences supported by the LatticeXP2.
Table 14-6. Wake Up Sequences Supported by LatticeXP2
21 (Default)
Sequence
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
1
2
3
4
5
6
7
8
9
DONE
DONE
DONE
DONE
DONE
DONE
DONE
Phase T0
GOE, GWDIS, GSR
GOE
GOE
GOE
GOE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
GOE
GOE, GWDIS
GWDIS
GWDIS, GSR
GOE, GSR
GOE, GWDIS, GSR
GOE
GOE, GWDIS
GWDIS
GWDIS, GSR
GOE, GSR
Phase T1
14-11
LatticeXP2 sysCONFIG Usage Guide
GOE, GWDIS, GSR
GWDIS, GSR
GWDIS
GSR
GOE, GWDIS, GSR
GWDIS, GSR
GOE
DONE
DONE
DONE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GOE, GSR
GOE
GWDIS
Phase T2
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GOE, GWDIS, GSR
GOE
GOE, GWDIS, GSR
GSR
GOE
DONE
DONE
DONE
DONE
GWDIS
GWDIS, GSR
GWDIS, GSR
GOE, GSR
GWDIS
DONE
DONE
DONE
Phase T3
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