SC900841JVK Freescale Semiconductor, SC900841JVK Datasheet - Page 136
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SC900841JVK
Manufacturer Part Number
SC900841JVK
Description
IC POWER MGT 338-MAPBGA
Manufacturer
Freescale Semiconductor
Specifications of SC900841JVK
Applications
PC's, PDA's
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
338-TBGA
Input Voltage
2.8 V to 4.4 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Voltage - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC900841JVK
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
SC900841JVKR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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length) or a long (word length) frame sync, which is selected
by the VCELONGFS bit. The frame sync can also be inverted
by setting the VCEFSINV bit.
and Rx. The active slots used by the voice CODEC are
controlled by the VCETXSLOT[1:0] and VCERXSLOT [1:0]
bits. The short frame sync occurs 1 bit clock cycle before the
data MSB, whereas the long frame sync is aligned with the
MSB. For multiple time slots, an optional turn around time
delay of 1 bit clock cycle can be added in between the slots
by setting the VCETRNARND bit. Outside of the assigned
136
900841
FUNCTIONAL DEVICE OPERATION
AUDIO
The interface supports 1, 2, or 4 time slots per frame for Tx
MODE 1: Short Frame Sync, 1 Word
FS1
BCL1
RX1
TX1
MODE 2: Short Frame Sync, 2 Words
FS1
BCL1
RX1
TX1
MODE 3: Long Frame Sync, 2 Words
FS1
BCL1
RX1
TX1
Figure 68. Voice CODEC Serial Interface Timing Diagram Modes 1-3
Hi-
Z
Hi-
Z
Hi-
Z
Bit n
Bit n
Bit n
Bit n
Bit n
Bit n
Slot 0
Slot 0
Bit 2
Bit 2
Bit 0
Bit 0
Bit 0
Bit 0
Slot 0
Bit 1
Bit 1
Bit n
Bit n
Bit n
Bit n
Slot 1
Slot 1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
time slot, the transmit data line is tri-stated. The tri-state
enable can be controlled by the VCETSB bit. The word length
is controlled by the VCEWORDLEN[2:0] bits and the bit clock
frequency is set with the VCECLKFRQ[2:0] bits.
modes 5-6 will be used for the voice codec. The timing
diagrams for these modes are given in
Figure
TX1 driver of the voice codec port is tri-stated and the TX1
line itself may be driven by another device in the application.
In practice, only certain modes, defined as modes 1-3 and
Hi-
Z
Hi-
Z
Hi-
Z
69. Note that where the TX1 line is shown at Hi-Z, the
Analog Integrated Circuit Device Data
Bit n
Bit n
Bit n
Bit n
Bit n
Bit n
Slot 0
Freescale Semiconductor
Figure 68
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