LCMXO1200C-5TN144C LATTICE SEMICONDUCTOR, LCMXO1200C-5TN144C Datasheet - Page 6
LCMXO1200C-5TN144C
Manufacturer Part Number
LCMXO1200C-5TN144C
Description
MACHXO PLD FLASH, SCRAM 1.8V, SMD
Manufacturer
LATTICE SEMICONDUCTOR
Series
MachXOr
Datasheet
1.LCMXO1200C-5TN144C.pdf
(244 pages)
Specifications of LCMXO1200C-5TN144C
Cpld Type
FLASH
No. Of Macrocells
600
No. Of I/o's
113
Propagation Delay
3.6ns
Global Clock Setup Time
1.1ns
Frequency
600MHz
Supply Voltage Range
1.71V To 3.465V
Operating
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO1200C-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
PCB Layout Recommendations for BGA Packages
Section III. MachXO Family Handbook Revision History
HDL Design with Lattice Semiconductor FPGA Devices ................................................................................. 13-8
Technical Support Assistance........................................................................................................................ 13-17
Introduction ...................................................................................................................................................... 14-1
BGA Board Layout Recommendations ............................................................................................................ 14-1
BGA Breakout and Routing Examples ............................................................................................................. 14-2
PCB Fabrication Cost and Design Rule Considerations ................................................................................ 14-13
Advantages and Disadvantages of BGA Packaging ...................................................................................... 14-14
BGA Package Test and Assembly ................................................................................................................. 14-15
PCB Design Support ...................................................................................................................................... 14-18
Technical Support Assistance........................................................................................................................ 14-18
Revision History ............................................................................................................................................. 14-19
Revision History ............................................................................................................................................... 15-1
State Encoding Methodologies for State Machines ................................................................................ 13-3
Coding Styles for FSM ............................................................................................................................ 13-5
Using Pipelines in the Designs................................................................................................................ 13-6
Comparing IF statement and CASE statement ....................................................................................... 13-7
Avoiding Non-intentional Latches............................................................................................................ 13-8
Lattice Semiconductor FPGA Synthesis Library ..................................................................................... 13-8
Implementing Multiplexers .................................................................................................................... 13-10
Clock Dividers ....................................................................................................................................... 13-10
Register Control Signals ....................................................................................................................... 13-12
Use PIC Features.................................................................................................................................. 13-14
Implementation of Memories................................................................................................................. 13-16
Preventing Logic Replication and Limited Fanout................................................................................. 13-16
Use ispLEVER Project Navigator Results for Device Utilization and Performance .............................. 13-17
64-ball csBGA BGA Breakout and Routing Example.............................................................................. 14-4
64-ball ucBGA BGA Breakout and Routing Example.............................................................................. 14-5
100-ball csBGA BGA Breakout and Routing Examples .......................................................................... 14-6
132-ball csBGA BGA Breakout Examples .............................................................................................. 14-8
144-ball csBGA BGA Breakout Examples ............................................................................................ 14-10
256-ball caBGA BGA Breakout Examples ............................................................................................ 14-12
5
MachXO Family Handbook
Table of Contents
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