LPC1113FBD48/301 NXP Semiconductors, LPC1113FBD48/301 Datasheet - Page 24
![MCU, 32BIT, 24K FLASH, CORTEX-M0, 48LQFP](/photos/19/0/190032/ge48lqfp05-40_sml.jpg)
LPC1113FBD48/301
Manufacturer Part Number
LPC1113FBD48/301
Description
MCU, 32BIT, 24K FLASH, CORTEX-M0, 48LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1111FHN33101.pdf
(66 pages)
Specifications of LPC1113FBD48/301
Controller Family/series
ARM Cortex-M0
No. Of I/o's
42
Ram Memory Size
8KB
Cpu Speed
50MHz
No. Of Timers
4
Core Size
32bit
Program Memory Size
24KB
Oscillator Type
External, Internal
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1113FBD48/301
Manufacturer:
NXP
Quantity:
5 600
Company:
Part Number:
LPC1113FBD48/301,1
Manufacturer:
NXP
Quantity:
1 250
Company:
Part Number:
LPC1113FBD48/301,1
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC1111_12_13_14
Product data sheet
7.10.1 Features
7.12.1 Features
7.11.1 Features
7.12 General purpose external event counter/timers
7.11 10-bit ADC
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The LPC1111/12/13/14 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
The LPC1111/12/13/14 includes two 32-bit counter/timers and two 16-bit counter/timers.
The counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
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The I
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V
10-bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
2
C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
2
2
2
C-interface is a standard I
C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 February 2011
DD
.
2
C-bus compliant interface with open-drain pins. The
32-bit ARM Cortex-M0 microcontroller
2
LPC1111/12/13/14
C is a multi-master bus and can be
© NXP B.V. 2011. All rights reserved.
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