LPC1113FBD48/301 NXP Semiconductors, LPC1113FBD48/301 Datasheet - Page 25
![MCU, 32BIT, 24K FLASH, CORTEX-M0, 48LQFP](/photos/19/0/190032/ge48lqfp05-40_sml.jpg)
LPC1113FBD48/301
Manufacturer Part Number
LPC1113FBD48/301
Description
MCU, 32BIT, 24K FLASH, CORTEX-M0, 48LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1111FHN33101.pdf
(66 pages)
Specifications of LPC1113FBD48/301
Controller Family/series
ARM Cortex-M0
No. Of I/o's
42
Ram Memory Size
8KB
Cpu Speed
50MHz
No. Of Timers
4
Core Size
32bit
Program Memory Size
24KB
Oscillator Type
External, Internal
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1113FBD48/301
Manufacturer:
NXP
Quantity:
5 600
Company:
Part Number:
LPC1113FBD48/301,1
Manufacturer:
NXP
Quantity:
1 250
Company:
Part Number:
LPC1113FBD48/301,1
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC1111_12_13_14
Product data sheet
7.14.1 Features
7.13 System tick timer
7.14 Watchdog timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
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Counter or timer operation.
One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of Watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 4 — 10 February 2011
× 4.
cy(WDCLK)
× 256 × 4) to (T
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
cy(WDCLK)
× 2
© NXP B.V. 2011. All rights reserved.
24
× 4) in
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