UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 199
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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7.4.2 Square-wave output operation
TO0n pin by setting the 16-bit timer output control register 0n (TOC0n) to 03H.
CR00n), the counting operation is started in synchronization with the count clock.
(INTTM00n) is generated, and TO0n output is inverted. This TO0n output that is inverted at fixed intervals enables
TO0n to output a square wave.
When 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1), a square wave can be output from the
When TMC0n3 and TMC0n2 are set to 11 (count clear & start mode entered upon a match between TM0n and
When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H, an interrupt signal
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
Remark n = 0:
Compare match interrupt
Count clock
(TMC0n3, TMC0n2)
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
Compare register
TMC0n3, TMC0n2
n = 0, 1:
Operable bits
TM0n register
Operable bits
TO0n output
(INTTM00n)
Figure 7-21. Basic Timing Example of Square-Wave Output Operation
(CR00n)
0000H
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Figure 7-20. Block Diagram of Square-Wave Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
00
Interval
(N + 1)
16-bit counter (TM0n)
User’s Manual U17260EJ6V0UD
CR00n register
Clear
N
Match signal
Interval
(N + 1)
N
11
N
Interval
(N + 1)
controller
Output
INTTM00n signal
N
TO0n output
Interval
(N + 1)
N
TO0n pin
199
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