UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 209
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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This is an application example where the width set to CR00n (4 clocks in this example) is to be output from the
TO0n pin when the count value has been captured & cleared.
The count value is captured to CR01n, a capture interrupt signal (INTTM01n) is generated, TM0n is cleared (to
0000H), and the TO0n output level is inverted when the valid edge of the TI00n pin is detected. When the count
value of TM0n is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM00n) is
generated and the TO0n output level is inverted.
Remark n = 0:
Capture & count clear input
Compare match interrupt
Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(TMC0n3, TMC0n2)
n = 0, 1:
Compare register
Capture interrupt
(TI00n pin input)
Capture register
(b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 0AH, CR00n = 0003H
TM0n register
Operable bits
TO0n output
(INTTM00n)
(INTTM01n)
µ
µ
(CR00n)
(CR01n)
(CR00n: Compare Register, CR01n: Capture Register) (2/2)
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
0003H
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
00
User’s Manual U17260EJ6V0UD
0003H
0000H
M
4
10
M
N
4
N
S
4
S
P
4
P
Q
Q
209
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