UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 321
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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(5) A/D port configuration register (ADPC)
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2
This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FF2FH
Symbol
ADPC
2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU
(PM2).
is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 35 CAUTIONS FOR WAIT.
ADPC3
0
0
0
0
0
0
0
0
1
7
0
Figure 13-9. Format of A/D Port Configuration Register (ADPC)
After reset: 00H
ADPC2
Other than above
0
0
0
0
1
1
1
1
0
6
0
ADPC1
CHAPTER 13 A/D CONVERTER
0
0
1
1
0
0
1
1
0
5
0
User’s Manual U17260EJ6V0UD
R/W
ADPC0
0
1
0
1
0
1
0
1
0
4
0
ANI7/
P27
Setting prohibited
A
A
A
A
A
A
A
A
D
ADPC3
Analog input (A)/digital I/O (D) switching
3
ANI6/
P26
A
A
A
A
A
A
A
D
D
ANI5/
P25
D
D
D
A
A
A
A
A
A
ADPC2
2
ANI4/
P24
D
D
D
D
A
A
A
A
A
ANI3/
P23
D
D
D
D
D
A
A
A
A
ADPC1
1
ANI2/
P22
A
A
A
D
D
D
D
D
D
ANI1/
P21
D
D
D
D
D
D
D
ADPC0
A
A
0
ANI0/
P20
A
D
D
D
D
D
D
D
D
321
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