AD7143ACPZ Analog Devices Inc, AD7143ACPZ Datasheet

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FEATURES Programmable capacitance-to-digital converter 25 ms update rate (@ maximum sequence length) Better than 1 fF resolution 8 capacitance sensor input channels No external RC tuning components required Automatic conversion sequencer On-chip automatic calibration logic Automatic compensation for environmental changes ...

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AD7143 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... Timing Specifications............................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and ...

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SPECIFICATIONS 2 3 − +85°C, unless otherwise noted Table 1. Parameter CAPACITANCE-TO-DIGITAL CONVERTER Update Rate Resolution CIN Input Range 1 No Missing Codes CIN Input Leakage Total Unadjusted ...

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AD7143 Table 2. Typical Average Current in Low Power Mode, V Low Power Mode Delay Decimation Rate 200 ms 128 256 400 ms 128 256 600 ms 128 256 800 ms 128 256 Table 3. Maximum Average Current in Low ...

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I C TIMING SPECIFICATIONS T = −40°C to +85° 2 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals timed A CC from a voltage level of 1.6 V. ...

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AD7143 ABSOLUTE MAXIMUM RATINGS Parameter VCC to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except 1 Supplies ESD Rating (Human Body Model) Operating Temperature Range Storage ...

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CIN2 Capacitance Sensor Input. 2 CIN3 Capacitance Sensor Input. 3 CIN4 Capacitance Sensor Input. 4 CIN5 Capacitance Sensor Input. 5 CIN6 Capacitance Sensor Input. 6 ...

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AD7143 TYPICAL PERFORMANCE CHARACTERISTICS 1000 980 DEVICE 1 960 DEVICE 3 940 920 DEVICE 2 900 880 860 840 820 2.7 2.8 2.9 3.0 3.1 3.2 V (V) CC Figure 4. Supply Current vs. Supply Voltage 180 LP_CONV_DELAY = 200ms ...

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TEMPERATURE (°C) Figure 10. Supply Current vs. Temperature 3.6V 3. –40 –20 0 ...

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AD7143 32900 32800 32700 32600 32500 32400 32300 PARASITIC 32200 CAPACITANCE 32100 32000 31900 PCB PARASITIC CAPACITANCE (pF) Figure 16. CDC Output Codes vs. Parasitic Capacitance Rev Page 10 of ...

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THEORY OF OPERATION The AD7143 is a capacitance-to-digital converter (CDC) with on-chip environmental compensation, intended for use in portable systems requiring high resolution user input. The internal circuitry consists of a 16-bit, ∑-Δ converter that converts a capacitive input signal ...

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AD7143 Complete Solution for Capacitance Sensing Analog Devices, Inc. provides a complete solution for capacitance sensing. The two main elements to the solution are the sensor PCB and the AD7143. If the application requires high resolution sensors, such as scroll ...

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CAPACITANCE SENSOR INPUT CONFIGURATION Each input connection from the external capacitance sensors to the AD7143 converter can be uniquely configured by using the registers in Table 38 and Table 39. These registers are used to configure input pin connection setups, ...

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AD7143 CAPACITIANCE-TO-DIGITAL CONVERTER The capacitance-to-digital converter on the AD7143 has a Σ-Δ architecture with 16-bit resolution. Eight possible inputs to the CDC are connected to the input of the converter through a switch matrix. The sampling frequency of the CDC ...

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STAGE7 STAGE6 STAGE5 STAGE4 STAGE3 STAGE2 STAGE1 STAGE0 CIN0 CIN1 CIN2 CIN3 Σ-Δ 16-BIT ADC CIN4 CIN5 CIN6 CIN7 Figure 23. CDC Conversion Stages The number of required conversion stages depends completely on the number of sensors attached to the ...

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AD7143 Low Power Mode CDC Conversion Sequence Time with Delay The frequency of each CDC conversion while operating in the low power automatic wake-up mode is controlled by using the LP_CONV_DELAY register located at Address 0x000[3:2], in addition to the ...

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NONCONTACT PROXIMITY DETECTION The AD7143 internal signal processing continuously monitors all capacitance sensors for noncontact proximity detection. This feature provides the ability to detect when a user is approaching a sensor, immediately disabling all internal calibration while the AD7143 is ...

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AD7143 USER APPROACHES SENSOR HERE CDC CONVERSION SEQUENCE (INTERNAL) PROXIMITY DETECTION (INTERNAL) CALIBRATION (INTERNAL) Figure 27. Full Power Mode Proximity Detection Example with FP_PROXIMITY_CNT ...

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USER APPROACHES SENSOR HERE USER LEAVES SENSOR AREA HERE CDC CONVERSION SEQUENCE (INTERNAL) PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED (INTERNAL) RECALIBRATION (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIME × LP_PROXIMITY_CNT × 4. CALDIS CONV_LP ...

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AD7143 Table 11. FF_SKIP_CNT Settings FF_SKIP_CNT Decimation = 128 0 1.525 × (SEQUENCE_STAGE_NUM + 3.072 × (SEQUENCE_STAGE_NUM + 4.608 × (SEQUENCE_STAGE_NUM + 6.144 × (SEQUENCE_STAGE_NUM + 7.68 × ...

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CDC STAGE_FF_WORD0 STAGE_FF_WORD1 STAGE_FF_WORD2 STAGE_FF_WORD3 STAGE_FF_WORD4 STAGE_FF_WORD5 STAGE_FF_WORD6 STAGE_FF_WORD7 BANK 3 REGISTERS 7 Σ WORD(N) BANK 3 REGISTERS PROXIMITY SW1 SLOW_FILTER_EN STAGE_SF_WORD0 COMPARATOR 3 WORD0 TO WORD1 STAGE_SF_WORD1 STAGE_SF_WORD2 STAGE_SF_WORD3 SLOW_FILTER_UPDATE_LVL STAGE_SF_WORD4 REGISTER 0x003 STAGE_SF_WORD5 ...

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AD7143 ENVIRONMENTAL CALIBRATION The AD7143 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels. Capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. ...

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CAPACITANCE SENSOR BEHAVIOR WITH CALIBRATION The AD7143 on-chip adaptive calibration algorithm prevents sensor detection errors, such as the one shown in Figure 34. This is achieved by monitoring the CDC ambient levels and readjusting the initial STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values ...

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AD7143 Table 12. Additional Information about Environmental Calibration and Adaptive Threshold Registers Register Location NEG_THRESHOLD_SENSITIVITY Bank 2 NEG_PEAK_DETECT Bank 2 POS_THRESHOLD_SENSITIVITY Bank 2 POS_PEAK_DETECT Bank 2 STAGE_OFFSET_LOW Bank 2 STAGE_OFFSET_HIGH Bank 2 STAGE_OFFSET_HIGH_CLAMP Bank 2 STAGE_OFFSET_LOW_CLAMP Bank 2 STAGE_SF_AMBIENT Bank ...

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ADAPTIVE THRESHOLD AND SENSITIVITY The AD7143 provides an on-chip self-learning adaptive threshold and sensitivity algorithm. This algorithm continu- ously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the ...

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AD7143 INTERRUPT OUTPUT The AD7143 has an interrupt output that triggers an interrupt service routine on the host processor. The INT signal is on Pin 14, and is an open-drain output. There are two types of interrupt events on the ...

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Table 13. Interrupt Mode Registers Interrupt Enable Interrupt Mode Register Address Sensor Touch Low 0x005 High 0x006 CDC Conversion Complete 0x007 STAGE0 STAGE1 STAGE2 CONVERSIONS INT 1 SERIAL READS NOTES 1. THIS IS AN EXAMPLE OF A CDC CONVERSION COMPLETE ...

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AD7143 SERIAL INTERFACE The AD7143 is available with a fixed address I interface COMPATIBLE INTERFACE The AD7143 supports the industry standard 2-wire I interface protocol. The two wires associated with the I the SCLK and the SDA ...

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Writing Data over the I C Bus The process for writing to the AD7143 over the I shown in Figure 39 and Figure 41. The device address is sent over the bus followed by the R/ W bit set ...

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AD7143 START AD7143 DEVICE ADDRESS SDA DEV DEV DEV DEV DEV SCLK AD7143 DEVICE ADDRESS SR DEV DEV A6 A5 USING REPEATED START ...

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PCB DESIGN GUIDELINES CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS Table 15. Parameter Distance from Edge of Any Sensor to Edge of Metal Object 1 Distance Between Sensor Edges Distance Between Bottom of Sensor Board and Controller Board or Metal Casing 2-Layer, ...

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AD7143 POWER-UP SEQUENCE When the AD7143 is powered up, the following sequence is recommended when initially developing the AD7143 and Host μC serial interface: 1. Turn on the power supplies to the AD7143. 2. Write to the Bank 2 registers ...

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TYPICAL APPLICATION CIRCUITS SCROLL WHEEL SENSOR PCB SDA 12 1 CIN2 VDRIVE 11 2 CIN3 AD7143 3 CIN4 GND 10 4 CIN5 VCC 9 10nF 2 Figure 46. Typical Application Circuit with I C Interface Rev Page 33 ...

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AD7143 REGISTER MAP The AD7143 address space is divided into three different register banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 47 illustrates the division of these three banks. Bank 1 registers contain control registers, CDC ...

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DETAILED REGISTER DESCRIPTIONS BANK 1 REGISTERS All addresses and default values are expressed in hexadecimal format. Table 16. PWR_CONTROL Register Address Data Bit Default Type 0x000 [1:0] 0 R/W [3:2] 0 [7:4] 0 [9:8] 0 [10] 0 [11] 0 [12] ...

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AD7143 Table 17. STAGE_CAL_EN Register Address Data Bit Default Type 0x001 [0] 0 R/W [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [11:8] 0 [13:12] 0 [15:14] 0 Name Description STAGE0_CAL_EN STAGE0 calibration enable ...

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Table 18. AMB_COMP_CTRL0 Register Address Data Bit Default Type 0x002 [3:0] 0 R/W [7:4] F [11:8] F [13:12] 0 [14] 0 [15] 0 Table 19. AMB_COMP_CTRL1 Register Address Data Bit Default Type 0x003 [7:0] 64 R/W [13:8] 1 [15:14] 0 ...

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AD7143 Table 21. STAGE_LOW_INT_EN Register Address Data Bit Default Type 0x005 [0] 0 R/W [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [11:8] 0 [15:12] 0 Name Description STAGE0_LOW_INT_EN STAGE0 low interrupt enable 0 ...

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Table 22. STAGE_HIGH_INT_EN Register Address Data Bit Default Type 0x006 [0] 0 R/W [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [15:8] Name Description STAGE0_HIGH_INT_EN STAGE0 high interrupt enable 0 = interrupt source disabled ...

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AD7143 Table 23. STAGE_COMPLETE_INT_EN Register Address Data Bit Default Type 0x007 [0] 0 R/W [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [11:8] 0 [12] 0 [15:13] Table 24. STAGE_LOW_LIMIT_INT Register Address Data Bit ...

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Table 25. STAGE_HIGH_LIMIT_INT Register Address Data Bit Default Type 0x009 [ [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [15:8] 1 Registers self-clear to 0 after readback, provided that the limits are ...

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AD7143 Table 27. CDC 16-Bit Conversion Data Registers Address Data Bit Default Type 0x00B [15: 0x00C [15: 0x00D [15: 0x00E [15: 0x00F [15: 0x010 [15: 0x011 [15:0] 0 ...

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BANK 2 REGISTERS All address values are expressed in hexadecimal format. Table 30. STAGE0 Configuration Registers Address Data Bit Default Type 0x080 [15:0] X R/W 0x081 [15:0] X R/W 0x082 [15:0] X R/W 0x083 [15:0] X R/W 0x084 [15:0] X ...

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AD7143 Table 33. STAGE3 Configuration Registers Address Data Bit Default Type 0x098 [15:0] X R/W 0x099 [15:0] X R/W 0x09A [15:0] X R/W 0x09B [15:0] X R/W 0x09C [15:0] X R/W 0x09D [15:0] X R/W 0x09E [15:0] X R/W 0x09F ...

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Table 37. STAGE7 Configuration Registers Address Data Bit Default Type 0x0B8 [15:0] X R/W 0x0B9 [15:0] X R/W 0x0BA [15:0] X R/W 0x0BB [15:0] X R/W 0x0BC [15:0] X R/W 0x0BD [15:0] X R/W 0x0BE [15:0] X R/W 0x0BF [15:0] ...

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AD7143 Table 39. STAGEX Detailed CIN7 Connection Setup Description Data Bit Default Type Name [1:0] X R/W CIN7_CONNECTION_SETUP [13:2] X R/W Unused [14] X R/W NEG_AFE_OFFSET_DISABLE [15] X R/W POS_AFE_OFFSET_DISABLE Table 40. STAGEX Detailed Offset Control Description ( ...

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BANK 3 REGISTERS All address values are expressed in hexadecimal format. Table 42. STAGE0 Results Registers Address Data Bit Default Type 0x0E0 [15:0] X R/W 0x0E1 [15:0] X R/W 0x0E2 [15:0] X R/W 0x0E3 [15:0] X R/W 0x0E4 [15:0] X ...

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AD7143 Table 43. STAGE1 Results Registers Address Data Bit Default Type 0x104 [15:0] X R/W 0x105 [15:0] X R/W 0x106 [15:0] X R/W 0x107 [15:0] X R/W 0x108 [15:0] X R/W 0x109 [15:0] X R/W 0x10A [15:0] X R/W 0x10B ...

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Table 44. STAGE2 Results Registers Address Data Bit Default Type 0x128 [15:0] X R/W 0x129 [15:0] X R/W 0x12A [15:0] X R/W 0x12B [15:0] X R/W 0x12C [15:0] X R/W 0x12D [15:0] X R/W 0x12E [15:0] X R/W 0x12F [15:0] ...

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AD7143 Table 45. STAGE3 Results Registers Address Data Bit Default Type 0x14C [15:0] X R/W 0x14D [15:0] X R/W 0x14E [15:0] X R/W 0x14F [15:0] X R/W 0x150 [15:0] X R/W 0x151 [15:0] X R/W 0x152 [15:0] X R/W 0x153 ...

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Table 46. STAGE4 Results Registers Address Data Bit Default Type 0x170 [15:0] X R/W 0x171 [15:0] X R/W 0x172 [15:0] X R/W 0x173 [15:0] X R/W 0x174 [15:0] X R/W 0x175 [15:0] X R/W 0x176 [15:0] X R/W 0x177 [15:0] ...

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AD7143 Table 47. STAGE5 Results Registers Address Data Bit Default Type 0x194 [15:0] X R/W 0x195 [15:0] X R/W 0x196 [15:0] X R/W 0x197 [15:0] X R/W 0x198 [15:0] X R/W 0x199 [15:0] X R/W 0x19A [15:0] X R/W 0x19B ...

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Table 48. STAGE6 Results Registers Address Data Bit Default Type 0x1B8 [15:0] X R/W 0x1B9 [15:0] X R/W 0x1BA [15:0] X R/W 0x1BB [15:0] X R/W 0x1BC [15:0] X R/W 0x1BD [15:0] X R/W 0x1BE [15:0] X R/W 0x1BF [15:0] ...

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AD7143 Table 49. STAGE7 Results Registers Address Data Bit Default Type 0x1DC [15:0] X R/W 0x1DD [15:0] X R/W 0x1DE [15:0] X R/W 0x1DF [15:0] X R/W 0x1E0 [15:0] X R/W 0x1E1 [15:0] X R/W 0x1E2 [15:0] X R/W 0x1E3 ...

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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range AD7143ACPZ-1REEL 1 −40°C to +85°C 1 AD7143ACPZ-1500RL7 −40°C to +85°C 1 EVAL-AD7143-1EBZ Pb-free part. 4.00 0.60 MAX BSC 3.75 BSC SQ 0.65 9 BSC TOP VIEW 1.95 BCS BOT TOM VIEW 0 ...

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AD7143 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...