CAT28F020G-90T CATALYST SEMICONDUCTOR, CAT28F020G-90T Datasheet
CAT28F020G-90T
Specifications of CAT28F020G-90T
Available stocks
Related parts for CAT28F020G-90T
CAT28F020G-90T Summary of contents
Page 1
Megabit CMOS Flash Memory FEATURES Fast read access time: 90/120 ns Low power CMOS dissipation: – Active max (CMOS/TTL levels) – Standby max (TTL levels) – Standby: 100 A max (CMOS levels) High speed programming: ...
Page 2
CAT28F020 PIN CONFIGURATION DIP Package ( ...
Page 3
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +130 C Storage Temperature ....................... – +150 C Voltage on Any Pin with (1) Respect to Ground ........... –2. Voltage on Pin A with 9 (1) ...
Page 4
CAT28F020 D.C. OPERATING CHARACTERISTICS V = +5V 10%, unless otherwise specified. (See Note 2) CC Symbol Parameter I Input Leakage Current LI I Output Leakage Current Standby Current CMOS SB1 Standby Current TTL SB2 ...
Page 5
SUPPLY CHARACTERISTICS ...
Page 6
CAT28F020 A.C. CHARACTERISTICS, Program/Erase Operation V = +5V 10%, unless otherwise specified. (See Note 6) CC JEDEC Standard Symbol Symbol Parameter t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time ...
Page 7
FUNCTION TABLE Mode CE Read V IL Output Disable V IL Standby V IH Signature (MFG Signature (Device Program/Erase V IL Write Cycle V IL Read Cycle V IL WRITE COMMAND TABLE Commands are written ...
Page 8
CAT28F020 READ OPERATIONS Read Mode A Read operation is performed with both CE and OE low and with WE high. V can be either high or low, PP however high, the Set READ command has to PP ...
Page 9
WRITE OPERATIONS The following operations are initiated by observing the sequence specified in the Write Command Table. Read Mode The device can be put into a standard READ mode by initiating a write cycle with 00H on the data bus. ...
Page 10
CAT28F020 (1) Figure 5. Chip Erase Algorithm START ERASURE APPLY V PPH PROGRAM ALL BYTES TO 00H INITIALIZE ADDRESS INITIALIZE PLSCNT = 0 WRITE ERASE SETUP COMMAND WRITE ERASE COMMAND TIME OUT 10ms WRITE ERASE VERIFY COMMAND TIME OUT 6 ...
Page 11
Erase-Verify Mode The Erase-verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. Programming Mode The programming operation is initiated using the pro- gramming algorithm of Figure 7. During the first ...
Page 12
CAT28F020 Figure 7. Programming Algorithm START PROGRAMMING APPLY V PPH INITIALIZE ADDRESS PLSCNT = 0 WRITE SETUP PROG. COMMAND WRITE PROG. CMD ADDR AND DATA TIME OUT 10 s WRITE PROGRAM VERIFY COMMAND TIME OUT 6 s READ DATA FROM ...
Page 13
Abort/Reset An Abort/Reset command is available to allow the user to safely abort an erase or program sequence. Two consecutive program cycles with FFH on the data bus will abort an erase or a program operation. The abort/ reset operation ...
Page 14
CAT28F020 ALTERNATE CE CE CE-CONTROLLED WRITES CE CE JEDEC Standard Symbol Symbol Parameter t t Write Cycle Time AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH ...
Page 15
EXAMPLE OF ORDERING INFORMATION Prefix Device # CAT 28F020 Product Number Optional Package Company ID N: PLCC T: TSOP (8mmx20mm) TR: TSOP (Reverse Pinout) G: PLCC (Lead free, Halogen free) L: PDIP (Lead free, Halogen free) H: TSOP (Lead free, ...
Page 16
CAT28F020 REVISION HISTORY Date Revision Description 1-May-02 A Initial issue 10-Feb-04 B Change V 01-Jul-04 C Added Green Packages in all areas. 15-Oct-08 D Eliminate PDIP SnPb package. 17-Nov-08 E Change logo and fine print to ON Semiconductor 31-Jul-09 F ...