EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 657
EP9307-CR
Manufacturer Part Number
EP9307-CR
Description
IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CR
Rohs Compliant
NO
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1254
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Quantity
Price
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CIRRUS
Quantity:
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DS785UM1
21.1 Introduction
The I
ADCs/DACs, and the ARM Core. It consists of 3 transmitter channels and 3 receiver
channels. Each channel handles a single stereo stream. The transmitter and receiver are
completely independent of each other and are programmed separately. Each channel (RX
and TX) has its own set of addressable registers which allows access through the ARM APB
or DMA accesses.
Figure 21-1
controller.input and output signals.
The i2s_audioclk_mux section performs gating on the incoming audio clocks based on the
settings within the TX and RX clock configuration registers and delivers a known clock
definition to the rest of the I
2
S controller is used to stream serial audio data between the external I
gives an architectural overview of the I
DMA
Controller
ARM
Core
Figure 21-1. Architectural Overview of the I
lrck
sck
Memory
6 DMA Channels
AMBA APB
BUS
2
S controller.
I
Copyright 2007 Cirrus Logic
2
S
I2S_APB/
DMA IF
lrckr & sckr
to each RX
channel
2
S controller.
TX Channel 0
TX Channel 1
TX Channel 2
RX Channel 0
RX Channel 1
RX Channel 2
I2S_AudioClk_Mux
2
S Controller
lrckt & sckt to
each TX channel
Table 21-1
21I
2
S Controller
Chapter 21
sdo0
sdo1
sdo2
lists the I
2
sdi0
sdi1
sdi2
S CODECs’,
2
S
21-1
21
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