PIC16F747-E/ML Microchip Technology, PIC16F747-E/ML Datasheet - Page 127
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC16F747-E/ML
Manufacturer Part Number
PIC16F747-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F747-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF777 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 127 of 688
- Download datasheet (3Mb)
8.2
8.2.1
1997 Microchip Technology Inc.
INTCON Register
Control Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Generally devices have a minimum of three registers associated with interrupts. The INTCON
register which contains Global Interrupt Enable bit, GIE, as well as the Peripheral Interrupt
Enable bit, PEIE, and the PIE / PIR register pair which enable the peripheral interrupts and dis-
play the interrupt flag status.
The INTCON Register is a readable and writable register which contains various enable and flag
bits.
Register 8-1: INTCON Register
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
RBIE
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
RBIF
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
R/W-0
Note 1: In some devices, the RBIE bit may also be known as GPIE and the RBIF bit may be
Note 2: Some devices may not have this feature. For those devices this bit is reserved.
Note 3: In devices with only one peripheral interrupt, this bit may be EEIE or ADIE.
Note:
GIE
(1)
(1)
: RB Port Change Interrupt Flag bit
: RB Port Change Interrupt Enable bit
know as GPIF.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).This
feature allows for software polling.
PEIE
R/W-0
(3)
W = Writable bit
R/W-0
T0IE
INTE
R/W-0
Section 8. Interrupts
(2)
- n = Value at POR reset
RBIE
R/W-0
2)
(1,
R/W-0
T0IF
INTF
R/W-0
DS31008A-page 8-5
(2)
bit 0
RBIF
R/W-0
(1, 2)
8
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