PIC16F747-E/ML Microchip Technology, PIC16F747-E/ML Datasheet - Page 136
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC16F747-E/ML
Manufacturer Part Number
PIC16F747-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F747-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF777 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 136 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
8.6
DS31008A-page 8-14
Initialization
Example 8-4
is the value to write into the interrupt enable register.
Example 8-5
before they are used. For debugging ease, it may help if macros are placed in other files that are
included at assembly time. This allows the source to be viewed without all the clutter of the
required macros. These files must be included before the macro is used, but it simplifies debug-
ging, if all include files are done at the top of the source file.
Example 8-7
saving and restoring of registers before the execution of the interrupt code.
Example 8-4: Initialization and Enabling of Interrupts
Example 8-5: Register Saving / Restoring as Macros
PIE1_MASK1
PUSH_MACRO
;
POP_MACRO
MOVWF
SWAPF
MOVWF
ENDM
SWAPF
MOVWF
SWAPF
SWAPF
ENDM
:
:
CLRF
CLRF
CLRF
BSF
MOVLW
MOVWF
BCF
BSF
shows the initialization and enabling of device interrupts, where PIE1_MASK1 value
shows a typical Interrupt Service Routine structure. This ISR uses macros for the
shows how to create macro definitions for functions. Macros must be defined
EQU B‘01101010’
STATUS
INTCON
PIR1
STATUS, RP0
PIE1_MASK1
PIE1
STATUS, RP0
INTCON, GIE
MACRO
W_TEMP
STATUS,W
STATUS_TEMP
MACRO
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
; Bank0
; Disable interrupts and clear some flags
; Clear all flag bits
; Bank1
; This is the initial masking for PIE1
;
; Bank0
; Enable Interrupts
; This Macro Saves register contents
; Copy W to a Temporary Register
;
; Swap STATUS nibbles and place
;
; Save STATUS to a Temporary register
;
; End this Macro
; This Macro Restores register contents
; Swap original STATUS register value
;
; Restore STATUS register from
;
; Swap W_Temp nibbles and return
;
; Swap W_Temp to W to restore original
;
; End this Macro
; This is the Interrupt Enable
;
regardless of current bank
into W register
in Bank0
into W (restores original bank)
W register
value to W_Temp
W value without affecting STATUS
Register mask value
Example 8-6
1997 Microchip Technology Inc.
shows this structure.
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